[PATCH] D87214: [X86] Use the same sequence for i128 ISD::ABS on 64-bit targets as we use for i64 on 32-bit targets.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG01b3e1675754: [X86] Use the same sequence for i128 ISD::ABS on 64-bit targets as we use for… (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D87214?vs=290156&id=290336#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87214/new/

https://reviews.llvm.org/D87214

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/abs.ll
  llvm/test/CodeGen/X86/iabs.ll


Index: llvm/test/CodeGen/X86/iabs.ll
===================================================================
--- llvm/test/CodeGen/X86/iabs.ll
+++ llvm/test/CodeGen/X86/iabs.ll
@@ -191,13 +191,14 @@
 ;
 ; X64-LABEL: test_i128:
 ; X64:       # %bb.0:
-; X64-NEXT:    xorl %edx, %edx
+; X64-NEXT:    movq %rsi, %rdx
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    negq %rax
-; X64-NEXT:    sbbq %rsi, %rdx
-; X64-NEXT:    testq %rsi, %rsi
-; X64-NEXT:    cmovnsq %rdi, %rax
-; X64-NEXT:    cmovnsq %rsi, %rdx
+; X64-NEXT:    movq %rsi, %rcx
+; X64-NEXT:    sarq $63, %rcx
+; X64-NEXT:    addq %rcx, %rax
+; X64-NEXT:    adcq %rcx, %rdx
+; X64-NEXT:    xorq %rcx, %rax
+; X64-NEXT:    xorq %rcx, %rdx
 ; X64-NEXT:    retq
   %tmp1neg = sub i128 0, %a
   %b = icmp sgt i128 %a, -1
Index: llvm/test/CodeGen/X86/abs.ll
===================================================================
--- llvm/test/CodeGen/X86/abs.ll
+++ llvm/test/CodeGen/X86/abs.ll
@@ -132,13 +132,14 @@
 define i128 @test_i128(i128 %a) nounwind {
 ; X64-LABEL: test_i128:
 ; X64:       # %bb.0:
-; X64-NEXT:    xorl %edx, %edx
+; X64-NEXT:    movq %rsi, %rdx
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    negq %rax
-; X64-NEXT:    sbbq %rsi, %rdx
-; X64-NEXT:    testq %rsi, %rsi
-; X64-NEXT:    cmovnsq %rdi, %rax
-; X64-NEXT:    cmovnsq %rsi, %rdx
+; X64-NEXT:    movq %rsi, %rcx
+; X64-NEXT:    sarq $63, %rcx
+; X64-NEXT:    addq %rcx, %rax
+; X64-NEXT:    adcq %rcx, %rdx
+; X64-NEXT:    xorq %rcx, %rax
+; X64-NEXT:    xorq %rcx, %rdx
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: test_i128:
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -195,6 +195,8 @@
     setOperationAction(ISD::ABS            , MVT::i32  , Custom);
   }
   setOperationAction(ISD::ABS              , MVT::i64  , Custom);
+  if (Subtarget.is64Bit())
+    setOperationAction(ISD::ABS            , MVT::i128 , Custom);
 
   // Funnel shifts.
   for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
@@ -29719,9 +29721,12 @@
     return;
   }
   case ISD::ABS: {
-    assert(N->getValueType(0) == MVT::i64 &&
+    assert((Subtarget.is64Bit() || N->getValueType(0) == MVT::i64) &&
            "Unexpected type (!= i64) on ABS.");
-    MVT HalfT = MVT::i32;
+    assert((!Subtarget.is64Bit() || N->getValueType(0) == MVT::i128) &&
+           "Unexpected type (!= i128) on ABS.");
+    MVT VT = N->getSimpleValueType(0);
+    MVT HalfT = VT == MVT::i128 ? MVT::i64 : MVT::i32;
     SDValue Lo, Hi, Tmp;
     SDVTList VTList = DAG.getVTList(HalfT, MVT::i1);
 
@@ -29737,7 +29742,7 @@
                      SDValue(Lo.getNode(), 1));
     Hi = DAG.getNode(ISD::XOR, dl, HalfT, Tmp, Hi);
     Lo = DAG.getNode(ISD::XOR, dl, HalfT, Tmp, Lo);
-    Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi));
+    Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi));
     return;
   }
   // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.


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