[PATCH] D87238: [ARM][LowOverheadLoops] Remove modifications to the correct element count register

[Sam Tebbs via Phabricator via llvm-commits]

samtebbs created this revision.
samtebbs added reviewers: samparker, SjoerdMeijer, dmgreen, simon_tatham, olista01, t.p.northover.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.
samtebbs requested review of this revision.

After my patch in D86087 <https://reviews.llvm.org/D86087>, code that now uses the mov operand rather than

  the vctp operand will no longer remove modifications to the vctp operand
  as they should. This patch fixes that by explicitly removing
  modifications to the vctp operand rather than the register used as the
  element count.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D87238

Files:
  llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll


Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
+++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
@@ -27,7 +27,6 @@
 ; CHECK-NEXT:    mov r3, r1
 ; CHECK-NEXT:  .LBB0_3: @ %do.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    subs r3, #4
 ; CHECK-NEXT:    vldrw.u32 q2, [r0], #16
 ; CHECK-NEXT:    vsub.f32 q2, q2, q1
 ; CHECK-NEXT:    vfma.f32 q0, q2, q2
Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
===================================================================
--- llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
+++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
@@ -173,11 +173,10 @@
   ; CHECK:   renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg
   ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
   ; CHECK:   renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1
-  ; CHECK:   $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
+  ; CHECK:   dead $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
   ; CHECK: bb.3.do.body:
   ; CHECK:   successors: %bb.3(0x7c000000), %bb.4(0x04000000)
-  ; CHECK:   liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3
-  ; CHECK:   renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
+  ; CHECK:   liveins: $lr, $q0, $q1, $r0, $r1, $r2
   ; CHECK:   renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg :: (load 16 from %ir.pSrc.addr.01, align 4)
   ; CHECK:   renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2
   ; CHECK:   renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 0, killed $noreg
Index: llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -527,7 +527,12 @@
   };
 
   MBB = VCTP->getParent();
-  if (auto *Def = RDA.getUniqueReachingMIDef(&MBB->back(), NumElements)) {
+  // Remove modifications to the element count since they have no purpose in a
+  // tail predicated loop. Explicitly refer to the vctp operand no matter which
+  // register NumElements has been assigned to, since that is what the
+  // modifications will be using
+  if (auto *Def = RDA.getUniqueReachingMIDef(&MBB->back(),
+                                             VCTP->getOperand(1).getReg())) {
     SmallPtrSet<MachineInstr*, 2> ElementChain;
     SmallPtrSet<MachineInstr*, 2> Ignore = { VCTP };
     unsigned ExpectedVectorWidth = getTailPredVectorWidth(VCTP->getOpcode());


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