[PATCH] D86684: [Refactor] Add the SchedHeuristic for Scheduler to allow platform customizing the heuristics

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang updated this revision to Diff 290069.
steven.zhang retitled this revision from "[NFC][Refactor] Add the SchedHeuristic for Scheduler to allow platform customizing the heuristics" to "[Refactor] Add the SchedHeuristic for Scheduler to allow platform customizing the heuristics".
steven.zhang added a comment.
Herald added a subscriber: asbirlea.

Address reviewer's comments.

The Scheduler Strategy owns the SchedHeuristics, and the PreRA/PostRA Scheduler owns the Scheduler Strategy. So, we are now registering the heuristics inside Scheduler, so that, the target don't need to subclass the Scheduler Strategy.

However, as the scheduler heuristics might change from scheduler regions(we will override the region policy before scheduling the region), we have to subclass the Scheduler to register heuristics whenever we are entering a new sched region.

Regarding to the compiling time, yes, the virtual dispatch will increase compiling time (63s ->76s) from my testing. Fix this by using function object, and I didn't see compiling time deg now.

Add two callbacks inside SchedHeuristic for target to maintain the internal state. @dmgreen Does it work for your downstream scheduler ?

- initialize  (It is called whenever we are entering a new sched region)
- update (It is called whenever an instruction is scheduled.)

This is the typical case for target to add new heuristic:

- subclass the SchedHeuristic and add private state as class member variable.
- SchedHeuristic::initialize()  Reset the state
- SchedHeuristic::update() Update the state with the new DAG
- SchedHeuristic::tryCandidate() Select the instruction according to current state.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D86684/new/

https://reviews.llvm.org/D86684

Files:
  llvm/include/llvm/CodeGen/MachineScheduler.h
  llvm/lib/CodeGen/MachineScheduler.cpp
  llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
  llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp
  llvm/lib/Target/PowerPC/PPCMachineScheduler.h
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/botheightreduce.mir
  llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
  llvm/test/CodeGen/PowerPC/rematerializable-instruction-machine-licm.ll
  llvm/test/CodeGen/PowerPC/sched-addi.ll
  llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
  llvm/test/CodeGen/PowerPC/sms-phi-1.ll
  llvm/test/CodeGen/PowerPC/sms-simple.ll
  llvm/test/CodeGen/PowerPC/stack-clash-dynamic-alloca.ll

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