[PATCH] D86268: [DAGTypeLegalizer] Handle ZERO_EXTEND of promoted integer in WidenVecRes_Convert.

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa updated this revision to Diff 289941.
jonpa added a comment.

> But we do not know anything about the relationship between C and B necessarily.

Added a check for this.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D86268/new/

https://reviews.llvm.org/D86268

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  llvm/test/CodeGen/SystemZ/vec-zext.ll


Index: llvm/test/CodeGen/SystemZ/vec-zext.ll
===================================================================
--- llvm/test/CodeGen/SystemZ/vec-zext.ll
+++ llvm/test/CodeGen/SystemZ/vec-zext.ll
@@ -92,3 +92,19 @@
   ret <8 x i16> %z
 }
 
+define <2 x i32> @fun11(<2 x i64> %Arg1, <2 x i64> %Arg2) {
+; CHECK-LABEL: fun11:
+; CHECK:      vgbm    %v0, 0
+; CHECK-NEXT: vceqg   %v1, %v24, %v0
+; CHECK-NEXT: vceqg   %v0, %v26, %v0
+; CHECK-NEXT: vo      %v0, %v1, %v0
+; CHECK-NEXT: vrepig  %v1, 1
+; CHECK-NEXT: vn      %v0, %v0, %v1
+; CHECK-NEXT: vpkg    %v24, %v0, %v0
+; CHECK-NEXT: br      %r14
+  %i3 = icmp eq <2 x i64> %Arg1, zeroinitializer
+  %i5 = icmp eq <2 x i64> %Arg2, zeroinitializer
+  %i6 = or <2 x i1> %i3, %i5
+  %i7 = zext <2 x i1> %i6 to <2 x i32>
+  ret <2 x i32> %i7
+}
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -3307,19 +3307,34 @@
 }
 
 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
+  LLVMContext &Ctx = *DAG.getContext();
   SDValue InOp = N->getOperand(0);
   SDLoc DL(N);
 
-  EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+  EVT WidenVT = TLI.getTypeToTransformTo(Ctx, N->getValueType(0));
   unsigned WidenNumElts = WidenVT.getVectorNumElements();
 
   EVT InVT = InOp.getValueType();
-  EVT InEltVT = InVT.getVectorElementType();
-  EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
 
   unsigned Opcode = N->getOpcode();
-  unsigned InVTNumElts = InVT.getVectorNumElements();
   const SDNodeFlags Flags = N->getFlags();
+
+  // Handle the case of ZERO_EXTEND where the promoted InVT element size does
+  // not equal that of WidenVT.
+  if (N->getOpcode() == ISD::ZERO_EXTEND &&
+      getTypeAction(InVT) == TargetLowering::TypePromoteInteger &&
+      TLI.getTypeToTransformTo(Ctx, InVT).getScalarSizeInBits() !=
+      WidenVT.getScalarSizeInBits()) {
+    InOp = ZExtPromotedInteger(InOp);
+    InVT = InOp.getValueType();
+    if (WidenVT.getScalarSizeInBits() < InVT.getScalarSizeInBits())
+      Opcode = ISD::TRUNCATE;
+  }
+
+  EVT InEltVT = InVT.getVectorElementType();
+  EVT InWidenVT = EVT::getVectorVT(Ctx, InEltVT, WidenNumElts);
+  unsigned InVTNumElts = InVT.getVectorNumElements();
+
   if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
     InOp = GetWidenedVector(N->getOperand(0));
     InVT = InOp.getValueType();


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