[llvm] 4d536c6 - [x86] add tests for store merging; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2020-09-04T08:50:50-04:00
New Revision: 4d536c6da55d662b7aad8da71815d8cba7d44967

URL: https://github.com/llvm/llvm-project/commit/4d536c6da55d662b7aad8da71815d8cba7d44967
DIFF: https://github.com/llvm/llvm-project/commit/4d536c6da55d662b7aad8da71815d8cba7d44967.diff

LOG: [x86] add tests for store merging; NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/stores-merging.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/stores-merging.ll b/llvm/test/CodeGen/X86/stores-merging.ll
index 85a086503410..6d6796d1c902 100644
--- a/llvm/test/CodeGen/X86/stores-merging.ll
+++ b/llvm/test/CodeGen/X86/stores-merging.ll
@@ -479,6 +479,39 @@ define void @trunc_i32_to_i16(i32 %x, i16* %p) {
   ret void
 }
 
+define void @be_i32_to_i16(i32 %x, i16* %p0) {
+; CHECK-LABEL: be_i32_to_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movw %di, 2(%rsi)
+; CHECK-NEXT:    shrl $16, %edi
+; CHECK-NEXT:    movw %di, (%rsi)
+; CHECK-NEXT:    retq
+  %sh1 = lshr i32 %x, 16
+  %t0 = trunc i32 %x to i16
+  %t1 = trunc i32 %sh1 to i16
+  %p1 = getelementptr inbounds i16, i16* %p0, i64 1
+  store i16 %t0, i16* %p1, align 2
+  store i16 %t1, i16* %p0, align 2
+  ret void
+}
+
+define void @be_i32_to_i16_order(i32 %x, i16* %p0) {
+; CHECK-LABEL: be_i32_to_i16_order:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    shrl $16, %eax
+; CHECK-NEXT:    movw %ax, (%rsi)
+; CHECK-NEXT:    movw %di, 2(%rsi)
+; CHECK-NEXT:    retq
+  %sh1 = lshr i32 %x, 16
+  %t0 = trunc i32 %x to i16
+  %t1 = trunc i32 %sh1 to i16
+  %p1 = getelementptr inbounds i16, i16* %p0, i64 1
+  store i16 %t1, i16* %p0, align 2
+  store i16 %t0, i16* %p1, align 2
+  ret void
+}
+
 define void @trunc_i64_to_i8(i64 %x, i8* %p) {
 ; CHECK-LABEL: trunc_i64_to_i8:
 ; CHECK:       # %bb.0:
@@ -552,3 +585,36 @@ define void @trunc_i64_to_i32(i64 %x, i32* %p) {
   store i32 %t2, i32* %p1, align 4
   ret void
 }
+
+define void @be_i64_to_i32(i64 %x, i32* %p0) {
+; CHECK-LABEL: be_i64_to_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, 4(%rsi)
+; CHECK-NEXT:    shrq $32, %rdi
+; CHECK-NEXT:    movl %edi, (%rsi)
+; CHECK-NEXT:    retq
+  %sh1 = lshr i64 %x, 32
+  %t0 = trunc i64 %x to i32
+  %t1 = trunc i64 %sh1 to i32
+  %p1 = getelementptr inbounds i32, i32* %p0, i64 1
+  store i32 %t0, i32* %p1, align 4
+  store i32 %t1, i32* %p0, align 4
+  ret void
+}
+
+define void @be_i64_to_i32_order(i64 %x, i32* %p0) {
+; CHECK-LABEL: be_i64_to_i32_order:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    shrq $32, %rax
+; CHECK-NEXT:    movl %eax, (%rsi)
+; CHECK-NEXT:    movl %edi, 4(%rsi)
+; CHECK-NEXT:    retq
+  %sh1 = lshr i64 %x, 32
+  %t0 = trunc i64 %x to i32
+  %t1 = trunc i64 %sh1 to i32
+  %p1 = getelementptr inbounds i32, i32* %p0, i64 1
+  store i32 %t1, i32* %p0, align 4
+  store i32 %t0, i32* %p1, align 4
+  ret void
+}