[PATCH] D87112: [DAGCombiner] allow more store merging for non-i8 truncated ops

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: RKSimon, efriedma, dmgreen, craig.topper.
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This is a follow-up suggested in D86420 <https://reviews.llvm.org/D86420> - if we have a pair of stores in inverted order for the target endian, we can rotate the source bits into place.
The "be_i64_to_i16_order" test shows a limitation of the current function (which might be avoided if we integrate this function with the other cases in mergeConsecutiveStores). In the earlier "be_i64_to_i16" test, we skip the first 2 stores because we do not match the full set as consecutive or rotate-able, but then we reach the last 2 stores and see that they are an inverted pair of 16-bit stores. The "be_i64_to_i16_order" test alters the program order of the stores, so we miss matching the sub-pattern.


https://reviews.llvm.org/D87112

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/merge-trunc-store.ll
  llvm/test/CodeGen/X86/stores-merging.ll

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