[PATCH] D87071: [Scheduling] Add a mutation to schedule GOT indirect instructions close to each other for linker optimization

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: nemanjai, stefanp, jsji, qiucf, PowerPC.
Herald added subscribers: javed.absar, kbarton, hiraditya, MatzeB.
Herald added a project: LLVM.
steven.zhang requested review of this revision.

The linker optimization for pcrel load/store compiler side change has been added by D79864 <https://reviews.llvm.org/D79864>. However, we still failed to perform this optimization for some simple case:

  pld 3, m at got@pcrel(0), 1
  li 4, 4
  stw 4, 0(3)
  blr

And this is what linker want to do:

  10010600:	02 00 10 06 	pstw    r4,132008
  10010604:	04 00 80 38 	li      r4,4
  10010608:	a8 03 80 90
  1001060c:	00 00 00 60 	nop
  10010610:	20 00 80 4e 	blr

The `li 4, 4` here disable the optimization as the above transformation is wrong because we are define the r4 in betwwen pld and stw. So, we want to schedule such kind of instructions before the pld to avoid this happens.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D87071

Files:
  llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp
  llvm/lib/Target/PowerPC/PPCMachineScheduler.h
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll
  llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll
  llvm/test/CodeGen/PowerPC/pcrel-tail-calls.ll

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