[PATCH] D84403: [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag

Wed Sep 2 19:19:49 PDT 2020

mareko added a comment.

In D84403#2251541 <https://reviews.llvm.org/D84403#2251541>, @mbrkusanin wrote:

> In D84403#2249309 <https://reviews.llvm.org/D84403#2249309>, @mareko wrote:
>
>> In D84403#2248880 <https://reviews.llvm.org/D84403#2248880>, @mbrkusanin wrote:
>>
>>> In D84403#2248536 <https://reviews.llvm.org/D84403#2248536>, @mareko wrote:
>>>
>>>> This breaks LDS. LLVMSetAlignment(inst, 4) on loads and stores has no effect. The IR says "align 4", yet the backend still selects b128.
>>>
>>> On what subtargets? GFX9 and 10 should select b128 for align 4. That is the purpose of the patch. Are you saying it selects it for SI, CI or VI?
>>
>> On GFX10. Apparently b128 with align 4 doesn't work there.
>
> I've checked a couple Vulkan CTS tests that now produce b128 instructions for SDag and they work fine. I also did not find any regressions on others. Can you give us any more details? Or a test to reproduce the issue?

More information:

- (gfx9 hasn't been tested)
- gfx10.1 has the corruption in WGP mode only (CU mode works)
- gfx10.3 works

It looks like it's a gfx10.1 hw bug in WGP mode, so a fix or workaround is needed. The driver always uses WGP mode.

Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D84403