[PATCH] D86548: [SVE][CodeGen] Legalisation of truncate for scalable vectors

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:9081-9082
+      HalfVec0 = DAG.getUNDEF(WideVT);
+    else if (Vec0.getOpcode() == AArch64ISD::UZP1)
+      HalfVec0 = Vec0->getOperand(0);
+    else {
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paulwalker-arm wrote:
> FYI: This looks more like a DAGCombine.  Considering how much we're relying on UPK/UZP for legalisation I'm wondering if we should (separately from this patch) introduce common ISD nodes for these operations.  Assuming there isn't already a way to do combines for target nodes? What does @eli.friedman think?
We could split this into a combine, I guess?

You can run DAGCombines on target-specific nodes by just adding a case to AArch64TargetLowering::PerformDAGCombine, I think.

I think we should avoid adding new target-independent nodes that are only useful for scalable vectors if we don't need them in target-independent code; it's hard to tell what common nodes would actually be useful without another backend to use them.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D86548/new/

https://reviews.llvm.org/D86548