[PATCH] D87046: [PPC] Do not emit extswsli in 32BIT mode when using -mcpu=pwr9

[Zarko Todorovski via Phabricator via llvm-commits]

ZarkoCA created this revision.
ZarkoCA added reviewers: PowerPC, sfertile, cebowleratibm, Xiangling_L.
Herald added subscribers: llvm-commits, kbarton, hiraditya, nemanjai.
Herald added a project: LLVM.
ZarkoCA requested review of this revision.

It looks like in some circumstances when compiling with `-mcpu=pwr9` we create an EXTSWSLI node when which causes llc to fail. No such error occurs in pwr8 or lower.

I've found this to happen in 32BIT AIX and BE Linux. the cause seems to be that the default return in combineSHL is to create an EXTSWSLI node.  Adding a check for whether we are in PPC64 before that fixes the issue.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D87046

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll


Index: llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll
@@ -0,0 +1,31 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff \
+; RUN:     -mattr=-altivec -mcpu=pwr9 < %s | FileCheck %s --check-prefix=32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN:     -mattr=-altivec -mcpu=pwr9 < %s | FileCheck %s --check-prefix=32BIT
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN:     -mattr=-altivec -mcpu=pwr9 < %s | FileCheck %s --check-prefix=64BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:     -mattr=-altivec -mcpu=pwr9 < %s | FileCheck %s --check-prefix=64BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mattr=-altivec -mcpu=pwr9 < %s | FileCheck %s --check-prefix=64BIT
+
+define dso_local void @a(i32 %inta, i32 %intb, i64 %longint, i64* %sum_a) {
+entry:  
+
+  %add = add nsw i32 %inta, %intb
+  %conv = sext i32 %add to i64
+  %shl = shl nsw i64 %conv, 8
+  %add15 = add nsw i64 %longint, %shl
+  store i64 %add15, i64* %sum_a, align 8
+  ret void
+}
+
+; CHECK-LABEL:     .a
+
+; 32BIT:           srawi [[REG1:[0-9]+]], [[REG2:[0-9]+]]
+; 32BIT-NEXT:      rotlwi [[REG3:[0-9]+]], [[REG2]], [[REG3]]
+; 32BIT-NEXT:      slwi [[REG2]], [[REG2]], [[REG3]]
+; 32BIT-NEXT:      rlwimi [[REG3]], {{[0-9]+}}, [[REG3]], {{[0-9]+}}, {{[0-9]+}}
+
+; 64BIT:           extswsli {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} 
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -16080,8 +16080,10 @@
   if (ShiftBy.getValueType() == MVT::i64)
     ShiftBy = DCI.DAG.getConstant(CN1->getZExtValue(), DL, MVT::i32);
 
-  return DCI.DAG.getNode(PPCISD::EXTSWSLI, DL, MVT::i64, N0->getOperand(0),
-                         ShiftBy);
+  if (Subtarget.isPPC64())
+    return DCI.DAG.getNode(PPCISD::EXTSWSLI, DL, MVT::i64, N0->getOperand(0),
+                           ShiftBy);
+  return SDValue();
 }
 
 SDValue PPCTargetLowering::combineSRA(SDNode *N, DAGCombinerInfo &DCI) const {


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