[PATCH] D85956: [AARCH64][RegisterCoalescer] clang miscompiles zero-extension to long long

[John Brawn via Phabricator via llvm-commits]

john.brawn added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp:735
+    const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
+  if (MI->isCopy() && (DstRC->getID() == AArch64::GPR64RegClassID) &&
+      (SrcRC == DstRC) && MI->getOperand(0).getSubReg())
----------------
We should have a comment here explaining why coalescing is incorrect in this case. Also I'm not sure if the SrcRC == DstRC is correct here, as the implicit zeroing on subregister write doesn't depend on what the source register is.


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  https://reviews.llvm.org/D85956/new/

https://reviews.llvm.org/D85956