[PATCH] D71767: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 2/2].

[Paul Walker via Phabricator via llvm-commits]

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With the exception of VSELECT lowering, which is being worked under D85364 <https://reviews.llvm.org/D85364>, everything else is available in master.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71767/new/

https://reviews.llvm.org/D71767