[PATCH] D86956: [AArch64LoadStoreOptimization] Bug fix in ldr to ldp conversion
Congzhe Cao via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 1 09:39:31 PDT 2020
congzhe created this revision.
congzhe added reviewers: fhahn, MatzeB, jmolloy, evandro.
congzhe added projects: Backend, fixing bugs in llvm, LLVM.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
congzhe requested review of this revision.
[AArch64LoadStoreOptimization] Bug fix in ldr to ldp conversion
When attempting to covert two ldr instructions to an ldp instruction, we should check if in between these two ldr instructions the base register has been modified. If that is the case then the conversion should not be performed because the second ldr is actually loading from a different address.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D86956
Files:
llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
Index: llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -1569,6 +1569,14 @@
!UsedRegUnits.available(getLdStRegOp(MI).getReg())) &&
!mayAlias(MI, MemInsns, AA)) {
+ // If the BaseReg has been modified, then cannot do the optimization.
+ // for example, in the following pattern
+ // ldr x1 [x2]
+ // ldr x2 [x3]
+ // ldr x4 [x2, #8],
+ // the first and third ldr cannot be converted to ldp x1, x4, [x2]
+ if (!ModifiedRegUnits.available(BaseReg))
+ return E;
Flags.setMergeForward(false);
Flags.clearRenameReg();
return MBBI;
@@ -1583,6 +1591,8 @@
!mayAlias(FirstMI, MemInsns, AA)) {
if (ModifiedRegUnits.available(getLdStRegOp(FirstMI).getReg())) {
+ if (!ModifiedRegUnits.available(BaseReg))
+ return E;
Flags.setMergeForward(true);
Flags.clearRenameReg();
return MBBI;
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