[PATCH] D70800: Fix AArch64 AAPCS frame record chain

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

I've had to revert this patch because it caused runtime failures when building spec2k/eon with `-march=armv8-a+sve -mllvm -aarch64-sve-vector-bits-min=256`.



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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp:3445-3446
   if (Bytes || (!Offset && SrcReg != DestReg)) {
-    assert((DestReg != AArch64::SP || Bytes % 16 == 0) &&
-           "SP increment/decrement not 16-byte aligned");
+    assert((DestReg != AArch64::SP || Bytes % 8 == 0) &&
+           "SP increment/decrement not 8-byte aligned");
     unsigned Opc = SetNZCV ? AArch64::ADDSXri : AArch64::ADDXri;
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I don't believe this is a safe fix for the issue mentioned when the patch was previously reverted by https://reviews.llvm.org/rG04879086b44348cad600a0a1ccbe1f7776cc3cf9.

The stack always being 16-byte align is a requirement for the AAPCS.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70800/new/

https://reviews.llvm.org/D70800