[PATCH] D86878: [AMDGPU] Fix a miscompile in add combine

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:10123
+
+    // Boolean operations are represented as a 32-bit sgpr, with bits set
+    // potentially even for inactive lanes. We cannot just strip zext here,
----------------
It's only 32-bit for wave32. This also doesn't consider scalar booleans


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:10128-10132
+    if (Opc == ISD::ZERO_EXTEND &&
+        (Cond.getOpcode() == ISD::AND || Cond.getOpcode() == ISD::OR ||
+         Cond.getOpcode() == ISD::XOR))
+      Cond = DAG.getSetCC(SL, MVT::i1, RHS, DAG.getConstant(0, SL, MVT::i32),
+                          ISD::SETNE);
----------------
I think this is the wrong place to fix this up. At this point we don't really know anything about lanes or registers, and the combine itself should already be correct


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D86878/new/

https://reviews.llvm.org/D86878