[PATCH] D86906: [AArch64LdStOptimzation] fix a bug in AArch64 Load Store Optimization

[Congzhe Cao via Phabricator via llvm-commits]

congzhe created this revision.
congzhe added reviewers: jmolloy, MatzeB, evandro, gberry, junbuml.
congzhe added projects: Backend, fixing bugs in llvm, LLVM.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
Herald added a reviewer: sscalpone.
congzhe requested review of this revision.

An ldp instruction cannot have two destination registers that are the same.

Current logic in AArch64 Load Store Optimization pass checks if the two destination registers are exactly the same, but did not check if one of them is a sub or super register of the other. This patch fixes the logic.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D86906

Files:
  llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  llvm/test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir

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