[PATCH] D86894: [SVE] Disable INSERT_SUBVECTOR DAGCombine for scalable vectors
Cameron McInally via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 31 13:29:29 PDT 2020
cameron.mcinally created this revision.
cameron.mcinally added reviewers: ctetreau, sdesmalen, fpetrogalli, c-rhodes, david-arm, kmclaughlin, paulwalker-arm.
Herald added subscribers: llvm-commits, psnobl, hiraditya, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.
cameron.mcinally requested review of this revision.
Looking for some input on this combine wrt scalable vectors. Right now, it uses code like this:
unsigned NumElts = VT.getVectorNumElements();
...
if ((NumElts % Scale) == 0 && (InsIdx % Scale) == 0) {
So it's obviously not compatible with scalable vectors right now.
Has anyone thought through overloading % for ElementCount? At first glance, it seems like we can't since we don't know the vscale. Am I missing something there?
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D86894
Files:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -20588,7 +20588,8 @@
EVT N0SrcSVT = N0Src.getValueType().getScalarType();
EVT N1SrcSVT = N1Src.getValueType().getScalarType();
if ((N0.isUndef() || N0SrcSVT == N1SrcSVT) &&
- N0Src.getValueType().isVector() && N1Src.getValueType().isVector()) {
+ N0Src.getValueType().isFixedLengthVector() &&
+ N1Src.getValueType().isFixedLengthVector()) {
EVT NewVT;
SDLoc DL(N);
SDValue NewIdx;
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D86894.289016.patch
Type: text/x-patch
Size: 662 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200831/8a90a0c8/attachment.bin>
More information about the llvm-commits
mailing list