[llvm] 9d3dc27 - AMDGPU: Fix broken switch braces

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-08-27T19:39:39-04:00
New Revision: 9d3dc276a698248b065d16c5b6b39939b9bb5281

URL: https://github.com/llvm/llvm-project/commit/9d3dc276a698248b065d16c5b6b39939b9bb5281
DIFF: https://github.com/llvm/llvm-project/commit/9d3dc276a698248b065d16c5b6b39939b9bb5281.diff

LOG: AMDGPU: Fix broken switch braces

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index dac9bdf2fb7c..f64a37830205 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -11408,7 +11408,7 @@ void SITargetLowering::computeKnownBitsForTargetInstr(
   const MachineInstr *MI = MRI.getVRegDef(R);
   switch (MI->getOpcode()) {
   case AMDGPU::G_INTRINSIC: {
-    switch (MI->getIntrinsicID())
+    switch (MI->getIntrinsicID()) {
     case Intrinsic::amdgcn_workitem_id_x:
       knownBitsForWorkitemID(*getSubtarget(), KB, Known, 0);
       break;
@@ -11427,6 +11427,7 @@ void SITargetLowering::computeKnownBitsForTargetInstr(
     }
     default:
       break;
+    }
   }
   }
 }