[llvm] f08bbde - Correctly revert "GlobalISel: Use & operator on KnownBits"

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-08-27T19:08:31-04:00
New Revision: f08bbde83f472c6f8a01d7a92cf712da30753b7b

URL: https://github.com/llvm/llvm-project/commit/f08bbde83f472c6f8a01d7a92cf712da30753b7b
DIFF: https://github.com/llvm/llvm-project/commit/f08bbde83f472c6f8a01d7a92cf712da30753b7b.diff

LOG: Correctly revert "GlobalISel: Use & operator on KnownBits"

I mis-resolved the revert through moving the code to another function.

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
    llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
index 3552abe998e0..185446f21ec3 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
@@ -110,8 +110,8 @@ void GISelKnownBits::computeKnownBitsMin(Register Src0, Register Src1,
   computeKnownBitsImpl(Src0, Known2, DemandedElts, Depth);
 
   // Only known if known in both the LHS and RHS.
-  Known.Zero &= Known.Zero;
-  Known.One &= Known.One;
+  Known.Zero &= Known2.Zero;
+  Known.One &= Known2.One;
 }
 
 void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir
index 8623546b2cc5..7bfca9a4972e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir
@@ -140,7 +140,9 @@ body:             |
     ; CHECK: %load0:_(s32) = G_LOAD %ptr0(p1) :: (load 4, addrspace 1)
     ; CHECK: %load1:_(s32) = G_ZEXTLOAD %ptr1(p1) :: (load 1, addrspace 1)
     ; CHECK: %smin:_(s32) = G_SMIN %load0, %load1
-    ; CHECK: $vgpr0 = COPY %smin(s32)
+    ; CHECK: %mask:_(s32) = G_CONSTANT i32 255
+    ; CHECK: %and:_(s32) = G_AND %smin, %mask
+    ; CHECK: $vgpr0 = COPY %and(s32)
     %ptr0:_(p1) = COPY $vgpr0_vgpr1
     %ptr1:_(p1) = COPY $vgpr2_vgpr3
     %load0:_(s32) = G_LOAD %ptr0 :: (load 4, addrspace 1, align 4)