[llvm] ee67963 - MIR: Infer not-SSA for subregister defs

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-08-27T16:56:16-04:00
New Revision: ee679638d75ca9a7f7d7be728fa069606dcc8ec7

URL: https://github.com/llvm/llvm-project/commit/ee679638d75ca9a7f7d7be728fa069606dcc8ec7
DIFF: https://github.com/llvm/llvm-project/commit/ee679638d75ca9a7f7d7be728fa069606dcc8ec7.diff

LOG: MIR: Infer not-SSA for subregister defs

It's possible to have a single virtual register def with a subreg
index that would pass the previous check, but it's not possible to
have a subregister def in SSA.

This is in preparation for adding stricter checks for SSA MIR.

Added: 
    llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir

Modified: 
    llvm/include/llvm/CodeGen/MachineRegisterInfo.h
    llvm/lib/CodeGen/MIRParser/MIRParser.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index 35aab5018fa4..756c6e5aa2c1 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -448,6 +448,19 @@ class MachineRegisterInfo {
     return ++DI == def_end();
   }
 
+  /// Returns the defining operand if there is exactly one operand defining the
+  /// specified register, otherwise nullptr.
+  MachineOperand *getOneDef(Register Reg) const {
+    def_iterator DI = def_begin(Reg);
+    if (DI == def_end()) // No defs.
+      return nullptr;
+
+    def_iterator OneDef = DI;
+    if (++DI == def_end())
+      return &*OneDef;
+    return nullptr; // Multiple defs.
+  }
+
   /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
   using use_iterator =
       defusechain_iterator<true, false, false, true, false, false>;

diff  --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 2e0b0e745e9e..badf5868c757 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -322,9 +322,14 @@ bool MIRParserImpl::parseMachineFunction(Module &M, MachineModuleInfo &MMI) {
 static bool isSSA(const MachineFunction &MF) {
   const MachineRegisterInfo &MRI = MF.getRegInfo();
   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
-    unsigned Reg = Register::index2VirtReg(I);
+    Register Reg = Register::index2VirtReg(I);
     if (!MRI.hasOneDef(Reg) && !MRI.def_empty(Reg))
       return false;
+
+    // Subregister defs are invalid in SSA.
+    const MachineOperand *RegDef = MRI.getOneDef(Reg);
+    if (RegDef && RegDef->getSubReg() != 0)
+      return false;
   }
   return true;
 }

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir b/llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
new file mode 100644
index 000000000000..10f0d1a94faf
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
@@ -0,0 +1,15 @@
+# REQUIRES: asserts
+# RUN: not --crash llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
+
+# CHECK: MachineFunctionProperties required by InstructionSelect pass are not met by function subreg_def_is_not_ssa.
+# CHECK-NEXT: Required properties: IsSSA
+# CHECK-NEXT: Current properties: NoPHIs
+# CHECK-NEXT: MachineFunctionProperties check failed
+
+---
+name: subreg_def_is_not_ssa
+body: |
+  bb.0:
+    %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+
+...