[llvm] 2259ce8 - [RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move
Alex Richardson via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 27 02:33:05 PDT 2020
Author: Alex Richardson
Date: 2020-08-27T10:32:22+01:00
New Revision: 2259ce8c9116e2fd057332a1ede08396e8d64d30
URL: https://github.com/llvm/llvm-project/commit/2259ce8c9116e2fd057332a1ede08396e8d64d30
DIFF: https://github.com/llvm/llvm-project/commit/2259ce8c9116e2fd057332a1ede08396e8d64d30.diff
LOG: [RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move
The isTriviallyRematerializable hook is only called for instructions that are
tagged as isAsCheapAsAMove. Since ADDI 0 is used for "mv" it should definitely
be marked with "isAsCheapAsAMove". This change avoids one stack spill in most of
the atomic-rmw.ll tests functions. It also avoids stack spills in two of our
out-of-tree CHERI tests.
ORI/XORI with zero may or may not be the same as a move micro-architecturally,
but since we are already doing it for register == x0, we might as well
do the same if the immediate is zero.
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D86480
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/test/CodeGen/RISCV/atomic-rmw.ll
llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
llvm/test/CodeGen/RISCV/vararg.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 7b6ea002c7b7..1973a3bc538b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -512,13 +512,15 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
const unsigned Opcode = MI.getOpcode();
- switch(Opcode) {
- default:
- break;
- case RISCV::ADDI:
- case RISCV::ORI:
- case RISCV::XORI:
- return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
+ switch (Opcode) {
+ default:
+ break;
+ case RISCV::ADDI:
+ case RISCV::ORI:
+ case RISCV::XORI:
+ return (MI.getOperand(1).isReg() &&
+ MI.getOperand(1).getReg() == RISCV::X0) ||
+ (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0);
}
return MI.isAsCheapAsAMove();
}
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index a84d50b5dca1..4b2e19504c40 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -2076,37 +2076,34 @@ define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lbu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 24
-; RV32I-NEXT: srai s0, a0, 24
-; RV32I-NEXT: addi s3, sp, 11
+; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB35_2
; RV32I-NEXT: .LBB35_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1
-; RV32I-NEXT: sb a1, 11(sp)
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a1, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB35_4
; RV32I-NEXT: .LBB35_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s0, a0, .LBB35_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: blt s1, a0, .LBB35_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB35_1
; RV32I-NEXT: .LBB35_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -2151,37 +2148,34 @@ define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lbu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 56
-; RV64I-NEXT: srai s0, a0, 56
-; RV64I-NEXT: addi s3, sp, 7
+; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB35_2
; RV64I-NEXT: .LBB35_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
-; RV64I-NEXT: sb a1, 7(sp)
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a1, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB35_4
; RV64I-NEXT: .LBB35_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s0, a0, .LBB35_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: blt s1, a0, .LBB35_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB35_1
; RV64I-NEXT: .LBB35_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -2230,37 +2224,34 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lbu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 24
-; RV32I-NEXT: srai s0, a0, 24
-; RV32I-NEXT: addi s3, sp, 11
+; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB36_2
; RV32I-NEXT: .LBB36_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1
-; RV32I-NEXT: sb a1, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a1, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB36_4
; RV32I-NEXT: .LBB36_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s0, a0, .LBB36_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: blt s1, a0, .LBB36_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB36_1
; RV32I-NEXT: .LBB36_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -2305,37 +2296,34 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lbu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 56
-; RV64I-NEXT: srai s0, a0, 56
-; RV64I-NEXT: addi s3, sp, 7
+; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB36_2
; RV64I-NEXT: .LBB36_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1
-; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a1, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB36_4
; RV64I-NEXT: .LBB36_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s0, a0, .LBB36_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: blt s1, a0, .LBB36_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB36_1
; RV64I-NEXT: .LBB36_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -2384,37 +2372,34 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lbu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 24
-; RV32I-NEXT: srai s0, a0, 24
-; RV32I-NEXT: addi s3, sp, 11
+; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB37_2
; RV32I-NEXT: .LBB37_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1
-; RV32I-NEXT: sb a1, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 3
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a1, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB37_4
; RV32I-NEXT: .LBB37_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s0, a0, .LBB37_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: blt s1, a0, .LBB37_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB37_1
; RV32I-NEXT: .LBB37_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -2459,37 +2444,34 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lbu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 56
-; RV64I-NEXT: srai s0, a0, 56
-; RV64I-NEXT: addi s3, sp, 7
+; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB37_2
; RV64I-NEXT: .LBB37_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1
-; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 3
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a1, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB37_4
; RV64I-NEXT: .LBB37_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s0, a0, .LBB37_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: blt s1, a0, .LBB37_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB37_1
; RV64I-NEXT: .LBB37_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -2538,37 +2520,34 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lbu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 24
-; RV32I-NEXT: srai s0, a0, 24
-; RV32I-NEXT: addi s3, sp, 11
+; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB38_2
; RV32I-NEXT: .LBB38_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1
-; RV32I-NEXT: sb a1, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a1, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB38_4
; RV32I-NEXT: .LBB38_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s0, a0, .LBB38_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: blt s1, a0, .LBB38_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB38_1
; RV32I-NEXT: .LBB38_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -2613,37 +2592,34 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lbu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 56
-; RV64I-NEXT: srai s0, a0, 56
-; RV64I-NEXT: addi s3, sp, 7
+; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB38_2
; RV64I-NEXT: .LBB38_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1
-; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a1, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB38_4
; RV64I-NEXT: .LBB38_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s0, a0, .LBB38_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: blt s1, a0, .LBB38_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB38_1
; RV64I-NEXT: .LBB38_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -2692,37 +2668,34 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lbu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 24
-; RV32I-NEXT: srai s0, a0, 24
-; RV32I-NEXT: addi s3, sp, 11
+; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB39_2
; RV32I-NEXT: .LBB39_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1
-; RV32I-NEXT: sb a1, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a1, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB39_4
; RV32I-NEXT: .LBB39_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s0, a0, .LBB39_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: blt s1, a0, .LBB39_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB39_1
; RV32I-NEXT: .LBB39_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -2767,37 +2740,34 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lbu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 56
-; RV64I-NEXT: srai s0, a0, 56
-; RV64I-NEXT: addi s3, sp, 7
+; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB39_2
; RV64I-NEXT: .LBB39_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1
-; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a1, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB39_4
; RV64I-NEXT: .LBB39_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s0, a0, .LBB39_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: blt s1, a0, .LBB39_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB39_1
; RV64I-NEXT: .LBB39_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -2846,37 +2816,34 @@ define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lbu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 24
-; RV32I-NEXT: srai s0, a0, 24
-; RV32I-NEXT: addi s3, sp, 11
+; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB40_2
; RV32I-NEXT: .LBB40_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1
-; RV32I-NEXT: sb a1, 11(sp)
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a1, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB40_4
; RV32I-NEXT: .LBB40_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a0, .LBB40_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: bge s1, a0, .LBB40_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB40_1
; RV32I-NEXT: .LBB40_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -2921,37 +2888,34 @@ define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lbu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 56
-; RV64I-NEXT: srai s0, a0, 56
-; RV64I-NEXT: addi s3, sp, 7
+; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB40_2
; RV64I-NEXT: .LBB40_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1
-; RV64I-NEXT: sb a1, 7(sp)
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a1, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB40_4
; RV64I-NEXT: .LBB40_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a0, .LBB40_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: bge s1, a0, .LBB40_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB40_1
; RV64I-NEXT: .LBB40_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -3000,37 +2964,34 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lbu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 24
-; RV32I-NEXT: srai s0, a0, 24
-; RV32I-NEXT: addi s3, sp, 11
+; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB41_2
; RV32I-NEXT: .LBB41_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1
-; RV32I-NEXT: sb a1, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a1, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB41_4
; RV32I-NEXT: .LBB41_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a0, .LBB41_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: bge s1, a0, .LBB41_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB41_1
; RV32I-NEXT: .LBB41_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -3075,37 +3036,34 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lbu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 56
-; RV64I-NEXT: srai s0, a0, 56
-; RV64I-NEXT: addi s3, sp, 7
+; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB41_2
; RV64I-NEXT: .LBB41_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1
-; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a1, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB41_4
; RV64I-NEXT: .LBB41_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a0, .LBB41_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: bge s1, a0, .LBB41_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB41_1
; RV64I-NEXT: .LBB41_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -3154,37 +3112,34 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lbu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 24
-; RV32I-NEXT: srai s0, a0, 24
-; RV32I-NEXT: addi s3, sp, 11
+; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB42_2
; RV32I-NEXT: .LBB42_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1
-; RV32I-NEXT: sb a1, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 3
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a1, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB42_4
; RV32I-NEXT: .LBB42_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a0, .LBB42_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: bge s1, a0, .LBB42_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB42_1
; RV32I-NEXT: .LBB42_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -3229,37 +3184,34 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lbu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 56
-; RV64I-NEXT: srai s0, a0, 56
-; RV64I-NEXT: addi s3, sp, 7
+; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB42_2
; RV64I-NEXT: .LBB42_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1
-; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 3
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a1, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB42_4
; RV64I-NEXT: .LBB42_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a0, .LBB42_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: bge s1, a0, .LBB42_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB42_1
; RV64I-NEXT: .LBB42_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -3308,37 +3260,34 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lbu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 24
-; RV32I-NEXT: srai s0, a0, 24
-; RV32I-NEXT: addi s3, sp, 11
+; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB43_2
; RV32I-NEXT: .LBB43_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1
-; RV32I-NEXT: sb a1, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a1, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB43_4
; RV32I-NEXT: .LBB43_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a0, .LBB43_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: bge s1, a0, .LBB43_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB43_1
; RV32I-NEXT: .LBB43_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -3383,37 +3332,34 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lbu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 56
-; RV64I-NEXT: srai s0, a0, 56
-; RV64I-NEXT: addi s3, sp, 7
+; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB43_2
; RV64I-NEXT: .LBB43_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1
-; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a1, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB43_4
; RV64I-NEXT: .LBB43_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a0, .LBB43_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: bge s1, a0, .LBB43_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB43_1
; RV64I-NEXT: .LBB43_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -3462,37 +3408,34 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lbu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 24
-; RV32I-NEXT: srai s0, a0, 24
-; RV32I-NEXT: addi s3, sp, 11
+; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: srai s1, a0, 24
; RV32I-NEXT: j .LBB44_2
; RV32I-NEXT: .LBB44_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
-; RV32I-NEXT: sb a1, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a1, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB44_4
; RV32I-NEXT: .LBB44_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
+; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a0, .LBB44_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: bge s1, a0, .LBB44_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB44_1
; RV32I-NEXT: .LBB44_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -3537,37 +3480,34 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lbu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 56
-; RV64I-NEXT: srai s0, a0, 56
-; RV64I-NEXT: addi s3, sp, 7
+; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: srai s1, a0, 56
; RV64I-NEXT: j .LBB44_2
; RV64I-NEXT: .LBB44_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1
-; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a1, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB44_4
; RV64I-NEXT: .LBB44_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
+; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a0, .LBB44_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: bge s1, a0, .LBB44_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB44_1
; RV64I-NEXT: .LBB44_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -3616,22 +3556,20 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
-; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255
-; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB45_2
; RV32I-NEXT: .LBB45_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1
-; RV32I-NEXT: sb a3, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a3, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB45_4
; RV32I-NEXT: .LBB45_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -3640,11 +3578,10 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bltu s1, a0, .LBB45_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1
-; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB45_1
; RV32I-NEXT: .LBB45_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -3684,22 +3621,20 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255
-; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB45_2
; RV64I-NEXT: .LBB45_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1
-; RV64I-NEXT: sb a3, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a3, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB45_4
; RV64I-NEXT: .LBB45_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -3708,11 +3643,10 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bltu s1, a0, .LBB45_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB45_1
; RV64I-NEXT: .LBB45_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -3756,22 +3690,20 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
-; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255
-; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB46_2
; RV32I-NEXT: .LBB46_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
-; RV32I-NEXT: sb a3, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a3, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB46_4
; RV32I-NEXT: .LBB46_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -3780,11 +3712,10 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bltu s1, a0, .LBB46_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
-; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB46_1
; RV32I-NEXT: .LBB46_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -3824,22 +3755,20 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255
-; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB46_2
; RV64I-NEXT: .LBB46_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
-; RV64I-NEXT: sb a3, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a3, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB46_4
; RV64I-NEXT: .LBB46_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -3848,11 +3777,10 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bltu s1, a0, .LBB46_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB46_1
; RV64I-NEXT: .LBB46_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -3896,22 +3824,20 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
-; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255
-; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB47_2
; RV32I-NEXT: .LBB47_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1
-; RV32I-NEXT: sb a3, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a3, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB47_4
; RV32I-NEXT: .LBB47_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -3920,11 +3846,10 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bltu s1, a0, .LBB47_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1
-; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB47_1
; RV32I-NEXT: .LBB47_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -3964,22 +3889,20 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255
-; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB47_2
; RV64I-NEXT: .LBB47_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1
-; RV64I-NEXT: sb a3, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a3, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB47_4
; RV64I-NEXT: .LBB47_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -3988,11 +3911,10 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bltu s1, a0, .LBB47_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB47_1
; RV64I-NEXT: .LBB47_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -4036,22 +3958,20 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
-; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255
-; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB48_2
; RV32I-NEXT: .LBB48_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1
-; RV32I-NEXT: sb a3, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a3, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB48_4
; RV32I-NEXT: .LBB48_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -4060,11 +3980,10 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bltu s1, a0, .LBB48_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1
-; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB48_1
; RV32I-NEXT: .LBB48_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -4104,22 +4023,20 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255
-; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB48_2
; RV64I-NEXT: .LBB48_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1
-; RV64I-NEXT: sb a3, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a3, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB48_4
; RV64I-NEXT: .LBB48_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -4128,11 +4045,10 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bltu s1, a0, .LBB48_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB48_1
; RV64I-NEXT: .LBB48_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -4176,22 +4092,20 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
-; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255
-; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB49_2
; RV32I-NEXT: .LBB49_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1
-; RV32I-NEXT: sb a3, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a3, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB49_4
; RV32I-NEXT: .LBB49_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -4200,11 +4114,10 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bltu s1, a0, .LBB49_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1
-; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB49_1
; RV32I-NEXT: .LBB49_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -4244,22 +4157,20 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255
-; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB49_2
; RV64I-NEXT: .LBB49_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1
-; RV64I-NEXT: sb a3, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a3, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB49_4
; RV64I-NEXT: .LBB49_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -4268,11 +4179,10 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bltu s1, a0, .LBB49_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB49_1
; RV64I-NEXT: .LBB49_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -4316,22 +4226,20 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
-; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255
-; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB50_2
; RV32I-NEXT: .LBB50_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
-; RV32I-NEXT: sb a3, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a3, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB50_4
; RV32I-NEXT: .LBB50_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -4340,11 +4248,10 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bgeu s1, a0, .LBB50_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
-; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB50_1
; RV32I-NEXT: .LBB50_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -4384,22 +4291,20 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255
-; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB50_2
; RV64I-NEXT: .LBB50_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
-; RV64I-NEXT: sb a3, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a3, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB50_4
; RV64I-NEXT: .LBB50_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -4408,11 +4313,10 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bgeu s1, a0, .LBB50_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB50_1
; RV64I-NEXT: .LBB50_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -4456,22 +4360,20 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
-; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255
-; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB51_2
; RV32I-NEXT: .LBB51_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
-; RV32I-NEXT: sb a3, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a3, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB51_4
; RV32I-NEXT: .LBB51_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -4480,11 +4382,10 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bgeu s1, a0, .LBB51_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
-; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB51_1
; RV32I-NEXT: .LBB51_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -4524,22 +4425,20 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255
-; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB51_2
; RV64I-NEXT: .LBB51_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
-; RV64I-NEXT: sb a3, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a3, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB51_4
; RV64I-NEXT: .LBB51_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -4548,11 +4447,10 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bgeu s1, a0, .LBB51_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB51_1
; RV64I-NEXT: .LBB51_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -4596,22 +4494,20 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
-; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255
-; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB52_2
; RV32I-NEXT: .LBB52_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
-; RV32I-NEXT: sb a3, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a3, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB52_4
; RV32I-NEXT: .LBB52_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -4620,11 +4516,10 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bgeu s1, a0, .LBB52_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
-; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB52_1
; RV32I-NEXT: .LBB52_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -4664,22 +4559,20 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255
-; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB52_2
; RV64I-NEXT: .LBB52_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
-; RV64I-NEXT: sb a3, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a3, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB52_4
; RV64I-NEXT: .LBB52_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -4688,11 +4581,10 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bgeu s1, a0, .LBB52_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB52_1
; RV64I-NEXT: .LBB52_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -4736,22 +4628,20 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
-; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255
-; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB53_2
; RV32I-NEXT: .LBB53_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
-; RV32I-NEXT: sb a3, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a3, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB53_4
; RV32I-NEXT: .LBB53_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -4760,11 +4650,10 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bgeu s1, a0, .LBB53_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
-; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB53_1
; RV32I-NEXT: .LBB53_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -4804,22 +4693,20 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255
-; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB53_2
; RV64I-NEXT: .LBB53_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
-; RV64I-NEXT: sb a3, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a3, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB53_4
; RV64I-NEXT: .LBB53_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -4828,11 +4715,10 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bgeu s1, a0, .LBB53_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB53_1
; RV64I-NEXT: .LBB53_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -4876,22 +4762,20 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0)
-; RV32I-NEXT: mv s3, a1
+; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: andi s1, a1, 255
-; RV32I-NEXT: addi s2, sp, 11
; RV32I-NEXT: j .LBB54_2
; RV32I-NEXT: .LBB54_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
-; RV32I-NEXT: sb a3, 11(sp)
+; RV32I-NEXT: sb a3, 15(sp)
+; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lb a3, 11(sp)
+; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB54_4
; RV32I-NEXT: .LBB54_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -4900,11 +4784,10 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-NEXT: bgeu s1, a0, .LBB54_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
-; RV32I-NEXT: mv a2, s3
+; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB54_1
; RV32I-NEXT: .LBB54_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -4944,22 +4827,20 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: andi s1, a1, 255
-; RV64I-NEXT: addi s2, sp, 7
; RV64I-NEXT: j .LBB54_2
; RV64I-NEXT: .LBB54_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
-; RV64I-NEXT: sb a3, 7(sp)
+; RV64I-NEXT: sb a3, 15(sp)
+; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lb a3, 7(sp)
+; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB54_4
; RV64I-NEXT: .LBB54_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -4968,11 +4849,10 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64I-NEXT: bgeu s1, a0, .LBB54_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB54_1
; RV64I-NEXT: .LBB54_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -7166,37 +7046,34 @@ define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lhu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 16
-; RV32I-NEXT: srai s0, a0, 16
-; RV32I-NEXT: addi s3, sp, 10
+; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB90_2
; RV32I-NEXT: .LBB90_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: sh a3, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB90_4
; RV32I-NEXT: .LBB90_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s0, a0, .LBB90_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: blt s1, a0, .LBB90_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB90_1
; RV32I-NEXT: .LBB90_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -7242,37 +7119,34 @@ define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lhu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 48
-; RV64I-NEXT: srai s0, a0, 48
-; RV64I-NEXT: addi s3, sp, 6
+; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB90_2
; RV64I-NEXT: .LBB90_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: sh a3, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB90_4
; RV64I-NEXT: .LBB90_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s0, a0, .LBB90_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: blt s1, a0, .LBB90_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB90_1
; RV64I-NEXT: .LBB90_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -7322,37 +7196,34 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lhu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 16
-; RV32I-NEXT: srai s0, a0, 16
-; RV32I-NEXT: addi s3, sp, 10
+; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB91_2
; RV32I-NEXT: .LBB91_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: sh a3, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB91_4
; RV32I-NEXT: .LBB91_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s0, a0, .LBB91_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: blt s1, a0, .LBB91_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB91_1
; RV32I-NEXT: .LBB91_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -7398,37 +7269,34 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lhu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 48
-; RV64I-NEXT: srai s0, a0, 48
-; RV64I-NEXT: addi s3, sp, 6
+; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB91_2
; RV64I-NEXT: .LBB91_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: sh a3, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB91_4
; RV64I-NEXT: .LBB91_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s0, a0, .LBB91_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: blt s1, a0, .LBB91_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB91_1
; RV64I-NEXT: .LBB91_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -7478,37 +7346,34 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lhu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 16
-; RV32I-NEXT: srai s0, a0, 16
-; RV32I-NEXT: addi s3, sp, 10
+; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB92_2
; RV32I-NEXT: .LBB92_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: sh a3, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 3
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB92_4
; RV32I-NEXT: .LBB92_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s0, a0, .LBB92_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: blt s1, a0, .LBB92_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB92_1
; RV32I-NEXT: .LBB92_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -7554,37 +7419,34 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lhu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 48
-; RV64I-NEXT: srai s0, a0, 48
-; RV64I-NEXT: addi s3, sp, 6
+; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB92_2
; RV64I-NEXT: .LBB92_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: sh a3, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 3
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB92_4
; RV64I-NEXT: .LBB92_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s0, a0, .LBB92_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: blt s1, a0, .LBB92_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB92_1
; RV64I-NEXT: .LBB92_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -7634,37 +7496,34 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lhu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 16
-; RV32I-NEXT: srai s0, a0, 16
-; RV32I-NEXT: addi s3, sp, 10
+; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB93_2
; RV32I-NEXT: .LBB93_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: sh a3, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB93_4
; RV32I-NEXT: .LBB93_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s0, a0, .LBB93_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: blt s1, a0, .LBB93_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB93_1
; RV32I-NEXT: .LBB93_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -7710,37 +7569,34 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lhu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 48
-; RV64I-NEXT: srai s0, a0, 48
-; RV64I-NEXT: addi s3, sp, 6
+; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB93_2
; RV64I-NEXT: .LBB93_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: sh a3, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB93_4
; RV64I-NEXT: .LBB93_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s0, a0, .LBB93_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: blt s1, a0, .LBB93_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB93_1
; RV64I-NEXT: .LBB93_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -7790,37 +7646,34 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lhu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 16
-; RV32I-NEXT: srai s0, a0, 16
-; RV32I-NEXT: addi s3, sp, 10
+; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB94_2
; RV32I-NEXT: .LBB94_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: sh a3, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB94_4
; RV32I-NEXT: .LBB94_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s0, a0, .LBB94_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: blt s1, a0, .LBB94_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB94_1
; RV32I-NEXT: .LBB94_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -7866,37 +7719,34 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lhu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 48
-; RV64I-NEXT: srai s0, a0, 48
-; RV64I-NEXT: addi s3, sp, 6
+; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB94_2
; RV64I-NEXT: .LBB94_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: sh a3, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB94_4
; RV64I-NEXT: .LBB94_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s0, a0, .LBB94_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: blt s1, a0, .LBB94_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB94_1
; RV64I-NEXT: .LBB94_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -7946,37 +7796,34 @@ define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lhu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 16
-; RV32I-NEXT: srai s0, a0, 16
-; RV32I-NEXT: addi s3, sp, 10
+; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB95_2
; RV32I-NEXT: .LBB95_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: sh a3, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB95_4
; RV32I-NEXT: .LBB95_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a0, .LBB95_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: bge s1, a0, .LBB95_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB95_1
; RV32I-NEXT: .LBB95_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -8022,37 +7869,34 @@ define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lhu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 48
-; RV64I-NEXT: srai s0, a0, 48
-; RV64I-NEXT: addi s3, sp, 6
+; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB95_2
; RV64I-NEXT: .LBB95_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: sh a3, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB95_4
; RV64I-NEXT: .LBB95_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a0, .LBB95_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: bge s1, a0, .LBB95_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB95_1
; RV64I-NEXT: .LBB95_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -8102,37 +7946,34 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lhu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 16
-; RV32I-NEXT: srai s0, a0, 16
-; RV32I-NEXT: addi s3, sp, 10
+; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB96_2
; RV32I-NEXT: .LBB96_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: sh a3, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB96_4
; RV32I-NEXT: .LBB96_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a0, .LBB96_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: bge s1, a0, .LBB96_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB96_1
; RV32I-NEXT: .LBB96_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -8178,37 +8019,34 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lhu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 48
-; RV64I-NEXT: srai s0, a0, 48
-; RV64I-NEXT: addi s3, sp, 6
+; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB96_2
; RV64I-NEXT: .LBB96_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: sh a3, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB96_4
; RV64I-NEXT: .LBB96_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a0, .LBB96_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: bge s1, a0, .LBB96_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB96_1
; RV64I-NEXT: .LBB96_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -8258,37 +8096,34 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lhu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 16
-; RV32I-NEXT: srai s0, a0, 16
-; RV32I-NEXT: addi s3, sp, 10
+; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB97_2
; RV32I-NEXT: .LBB97_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: sh a3, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 3
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB97_4
; RV32I-NEXT: .LBB97_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a0, .LBB97_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: bge s1, a0, .LBB97_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB97_1
; RV32I-NEXT: .LBB97_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -8334,37 +8169,34 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lhu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 48
-; RV64I-NEXT: srai s0, a0, 48
-; RV64I-NEXT: addi s3, sp, 6
+; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB97_2
; RV64I-NEXT: .LBB97_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: sh a3, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 3
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB97_4
; RV64I-NEXT: .LBB97_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a0, .LBB97_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: bge s1, a0, .LBB97_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB97_1
; RV64I-NEXT: .LBB97_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -8414,37 +8246,34 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lhu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 16
-; RV32I-NEXT: srai s0, a0, 16
-; RV32I-NEXT: addi s3, sp, 10
+; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB98_2
; RV32I-NEXT: .LBB98_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: sh a3, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB98_4
; RV32I-NEXT: .LBB98_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a0, .LBB98_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: bge s1, a0, .LBB98_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB98_1
; RV32I-NEXT: .LBB98_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -8490,37 +8319,34 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lhu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 48
-; RV64I-NEXT: srai s0, a0, 48
-; RV64I-NEXT: addi s3, sp, 6
+; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB98_2
; RV64I-NEXT: .LBB98_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: sh a3, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB98_4
; RV64I-NEXT: .LBB98_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a0, .LBB98_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: bge s1, a0, .LBB98_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB98_1
; RV64I-NEXT: .LBB98_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -8570,37 +8396,34 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s1, a0
-; RV32I-NEXT: lhu a1, 0(a0)
-; RV32I-NEXT: slli a0, s2, 16
-; RV32I-NEXT: srai s0, a0, 16
-; RV32I-NEXT: addi s3, sp, 10
+; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: srai s1, a0, 16
; RV32I-NEXT: j .LBB99_2
; RV32I-NEXT: .LBB99_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: sh a3, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5
-; RV32I-NEXT: mv a0, s1
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB99_4
; RV32I-NEXT: .LBB99_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
+; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a0, .LBB99_1
+; RV32I-NEXT: mv a2, a3
+; RV32I-NEXT: bge s1, a0, .LBB99_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: j .LBB99_1
; RV32I-NEXT: .LBB99_4: # %atomicrmw.end
-; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s3, 12(sp)
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -8646,37 +8469,34 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s1, a0
-; RV64I-NEXT: lhu a1, 0(a0)
-; RV64I-NEXT: slli a0, s2, 48
-; RV64I-NEXT: srai s0, a0, 48
-; RV64I-NEXT: addi s3, sp, 6
+; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: srai s1, a0, 48
; RV64I-NEXT: j .LBB99_2
; RV64I-NEXT: .LBB99_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: sh a3, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
-; RV64I-NEXT: mv a0, s1
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB99_4
; RV64I-NEXT: .LBB99_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
+; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a0, .LBB99_1
+; RV64I-NEXT: mv a2, a3
+; RV64I-NEXT: bge s1, a0, .LBB99_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB99_1
; RV64I-NEXT: .LBB99_4: # %atomicrmw.end
-; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -8727,24 +8547,22 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
-; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0
-; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB100_2
; RV32I-NEXT: .LBB100_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1
-; RV32I-NEXT: sh a1, 6(sp)
-; RV32I-NEXT: mv a0, s4
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: addi a1, sp, 10
+; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 6(sp)
+; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB100_4
; RV32I-NEXT: .LBB100_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -8757,7 +8575,6 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: j .LBB100_1
; RV32I-NEXT: .LBB100_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
@@ -8794,30 +8611,28 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i16_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: sd ra, 56(sp)
-; RV64I-NEXT: sd s0, 48(sp)
-; RV64I-NEXT: sd s1, 40(sp)
-; RV64I-NEXT: sd s2, 32(sp)
-; RV64I-NEXT: sd s3, 24(sp)
-; RV64I-NEXT: sd s4, 16(sp)
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp)
+; RV64I-NEXT: sd s0, 32(sp)
+; RV64I-NEXT: sd s1, 24(sp)
+; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0
-; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB100_2
; RV64I-NEXT: .LBB100_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
-; RV64I-NEXT: mv a0, s4
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
+; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB100_4
; RV64I-NEXT: .LBB100_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -8830,13 +8645,12 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: j .LBB100_1
; RV64I-NEXT: .LBB100_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s4, 16(sp)
-; RV64I-NEXT: ld s3, 24(sp)
-; RV64I-NEXT: ld s2, 32(sp)
-; RV64I-NEXT: ld s1, 40(sp)
-; RV64I-NEXT: ld s0, 48(sp)
-; RV64I-NEXT: ld ra, 56(sp)
-; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: ld s2, 16(sp)
+; RV64I-NEXT: ld s1, 24(sp)
+; RV64I-NEXT: ld s0, 32(sp)
+; RV64I-NEXT: ld ra, 40(sp)
+; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umax_i16_monotonic:
@@ -8877,24 +8691,22 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
-; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0
-; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB101_2
; RV32I-NEXT: .LBB101_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1
-; RV32I-NEXT: sh a1, 6(sp)
+; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2
-; RV32I-NEXT: mv a0, s4
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 6(sp)
+; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB101_4
; RV32I-NEXT: .LBB101_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -8907,7 +8719,6 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: j .LBB101_1
; RV32I-NEXT: .LBB101_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
@@ -8944,30 +8755,28 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i16_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: sd ra, 56(sp)
-; RV64I-NEXT: sd s0, 48(sp)
-; RV64I-NEXT: sd s1, 40(sp)
-; RV64I-NEXT: sd s2, 32(sp)
-; RV64I-NEXT: sd s3, 24(sp)
-; RV64I-NEXT: sd s4, 16(sp)
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp)
+; RV64I-NEXT: sd s0, 32(sp)
+; RV64I-NEXT: sd s1, 24(sp)
+; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0
-; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB101_2
; RV64I-NEXT: .LBB101_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
-; RV64I-NEXT: mv a0, s4
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB101_4
; RV64I-NEXT: .LBB101_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -8980,13 +8789,12 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: j .LBB101_1
; RV64I-NEXT: .LBB101_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s4, 16(sp)
-; RV64I-NEXT: ld s3, 24(sp)
-; RV64I-NEXT: ld s2, 32(sp)
-; RV64I-NEXT: ld s1, 40(sp)
-; RV64I-NEXT: ld s0, 48(sp)
-; RV64I-NEXT: ld ra, 56(sp)
-; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: ld s2, 16(sp)
+; RV64I-NEXT: ld s1, 24(sp)
+; RV64I-NEXT: ld s0, 32(sp)
+; RV64I-NEXT: ld ra, 40(sp)
+; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umax_i16_acquire:
@@ -9027,24 +8835,22 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
-; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0
-; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB102_2
; RV32I-NEXT: .LBB102_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1
-; RV32I-NEXT: sh a1, 6(sp)
+; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 3
-; RV32I-NEXT: mv a0, s4
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 6(sp)
+; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB102_4
; RV32I-NEXT: .LBB102_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -9057,7 +8863,6 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: j .LBB102_1
; RV32I-NEXT: .LBB102_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
@@ -9094,30 +8899,28 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i16_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: sd ra, 56(sp)
-; RV64I-NEXT: sd s0, 48(sp)
-; RV64I-NEXT: sd s1, 40(sp)
-; RV64I-NEXT: sd s2, 32(sp)
-; RV64I-NEXT: sd s3, 24(sp)
-; RV64I-NEXT: sd s4, 16(sp)
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp)
+; RV64I-NEXT: sd s0, 32(sp)
+; RV64I-NEXT: sd s1, 24(sp)
+; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0
-; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB102_2
; RV64I-NEXT: .LBB102_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 3
-; RV64I-NEXT: mv a0, s4
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB102_4
; RV64I-NEXT: .LBB102_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -9130,13 +8933,12 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: j .LBB102_1
; RV64I-NEXT: .LBB102_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s4, 16(sp)
-; RV64I-NEXT: ld s3, 24(sp)
-; RV64I-NEXT: ld s2, 32(sp)
-; RV64I-NEXT: ld s1, 40(sp)
-; RV64I-NEXT: ld s0, 48(sp)
-; RV64I-NEXT: ld ra, 56(sp)
-; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: ld s2, 16(sp)
+; RV64I-NEXT: ld s1, 24(sp)
+; RV64I-NEXT: ld s0, 32(sp)
+; RV64I-NEXT: ld ra, 40(sp)
+; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umax_i16_release:
@@ -9177,24 +8979,22 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
-; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0
-; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB103_2
; RV32I-NEXT: .LBB103_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1
-; RV32I-NEXT: sh a1, 6(sp)
+; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2
-; RV32I-NEXT: mv a0, s4
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 6(sp)
+; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB103_4
; RV32I-NEXT: .LBB103_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -9207,7 +9007,6 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: j .LBB103_1
; RV32I-NEXT: .LBB103_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
@@ -9244,30 +9043,28 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i16_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: sd ra, 56(sp)
-; RV64I-NEXT: sd s0, 48(sp)
-; RV64I-NEXT: sd s1, 40(sp)
-; RV64I-NEXT: sd s2, 32(sp)
-; RV64I-NEXT: sd s3, 24(sp)
-; RV64I-NEXT: sd s4, 16(sp)
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp)
+; RV64I-NEXT: sd s0, 32(sp)
+; RV64I-NEXT: sd s1, 24(sp)
+; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0
-; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB103_2
; RV64I-NEXT: .LBB103_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
-; RV64I-NEXT: mv a0, s4
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB103_4
; RV64I-NEXT: .LBB103_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -9280,13 +9077,12 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: j .LBB103_1
; RV64I-NEXT: .LBB103_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s4, 16(sp)
-; RV64I-NEXT: ld s3, 24(sp)
-; RV64I-NEXT: ld s2, 32(sp)
-; RV64I-NEXT: ld s1, 40(sp)
-; RV64I-NEXT: ld s0, 48(sp)
-; RV64I-NEXT: ld ra, 56(sp)
-; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: ld s2, 16(sp)
+; RV64I-NEXT: ld s1, 24(sp)
+; RV64I-NEXT: ld s0, 32(sp)
+; RV64I-NEXT: ld ra, 40(sp)
+; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umax_i16_acq_rel:
@@ -9327,24 +9123,22 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
-; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0
-; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB104_2
; RV32I-NEXT: .LBB104_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1
-; RV32I-NEXT: sh a1, 6(sp)
+; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5
-; RV32I-NEXT: mv a0, s4
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 6(sp)
+; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB104_4
; RV32I-NEXT: .LBB104_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -9357,7 +9151,6 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: j .LBB104_1
; RV32I-NEXT: .LBB104_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
@@ -9394,30 +9187,28 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i16_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: sd ra, 56(sp)
-; RV64I-NEXT: sd s0, 48(sp)
-; RV64I-NEXT: sd s1, 40(sp)
-; RV64I-NEXT: sd s2, 32(sp)
-; RV64I-NEXT: sd s3, 24(sp)
-; RV64I-NEXT: sd s4, 16(sp)
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp)
+; RV64I-NEXT: sd s0, 32(sp)
+; RV64I-NEXT: sd s1, 24(sp)
+; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0
-; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB104_2
; RV64I-NEXT: .LBB104_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
-; RV64I-NEXT: mv a0, s4
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB104_4
; RV64I-NEXT: .LBB104_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -9430,13 +9221,12 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: j .LBB104_1
; RV64I-NEXT: .LBB104_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s4, 16(sp)
-; RV64I-NEXT: ld s3, 24(sp)
-; RV64I-NEXT: ld s2, 32(sp)
-; RV64I-NEXT: ld s1, 40(sp)
-; RV64I-NEXT: ld s0, 48(sp)
-; RV64I-NEXT: ld ra, 56(sp)
-; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: ld s2, 16(sp)
+; RV64I-NEXT: ld s1, 24(sp)
+; RV64I-NEXT: ld s0, 32(sp)
+; RV64I-NEXT: ld ra, 40(sp)
+; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umax_i16_seq_cst:
@@ -9477,24 +9267,22 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
-; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0
-; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB105_2
; RV32I-NEXT: .LBB105_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1
-; RV32I-NEXT: sh a1, 6(sp)
-; RV32I-NEXT: mv a0, s4
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: addi a1, sp, 10
+; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 6(sp)
+; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB105_4
; RV32I-NEXT: .LBB105_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -9507,7 +9295,6 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: j .LBB105_1
; RV32I-NEXT: .LBB105_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
@@ -9544,30 +9331,28 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i16_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: sd ra, 56(sp)
-; RV64I-NEXT: sd s0, 48(sp)
-; RV64I-NEXT: sd s1, 40(sp)
-; RV64I-NEXT: sd s2, 32(sp)
-; RV64I-NEXT: sd s3, 24(sp)
-; RV64I-NEXT: sd s4, 16(sp)
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp)
+; RV64I-NEXT: sd s0, 32(sp)
+; RV64I-NEXT: sd s1, 24(sp)
+; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0
-; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB105_2
; RV64I-NEXT: .LBB105_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
-; RV64I-NEXT: mv a0, s4
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
+; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB105_4
; RV64I-NEXT: .LBB105_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -9580,13 +9365,12 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: j .LBB105_1
; RV64I-NEXT: .LBB105_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s4, 16(sp)
-; RV64I-NEXT: ld s3, 24(sp)
-; RV64I-NEXT: ld s2, 32(sp)
-; RV64I-NEXT: ld s1, 40(sp)
-; RV64I-NEXT: ld s0, 48(sp)
-; RV64I-NEXT: ld ra, 56(sp)
-; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: ld s2, 16(sp)
+; RV64I-NEXT: ld s1, 24(sp)
+; RV64I-NEXT: ld s0, 32(sp)
+; RV64I-NEXT: ld ra, 40(sp)
+; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umin_i16_monotonic:
@@ -9627,24 +9411,22 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
-; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0
-; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB106_2
; RV32I-NEXT: .LBB106_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1
-; RV32I-NEXT: sh a1, 6(sp)
+; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2
-; RV32I-NEXT: mv a0, s4
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 6(sp)
+; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB106_4
; RV32I-NEXT: .LBB106_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -9657,7 +9439,6 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: j .LBB106_1
; RV32I-NEXT: .LBB106_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
@@ -9694,30 +9475,28 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i16_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: sd ra, 56(sp)
-; RV64I-NEXT: sd s0, 48(sp)
-; RV64I-NEXT: sd s1, 40(sp)
-; RV64I-NEXT: sd s2, 32(sp)
-; RV64I-NEXT: sd s3, 24(sp)
-; RV64I-NEXT: sd s4, 16(sp)
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp)
+; RV64I-NEXT: sd s0, 32(sp)
+; RV64I-NEXT: sd s1, 24(sp)
+; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0
-; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB106_2
; RV64I-NEXT: .LBB106_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
-; RV64I-NEXT: mv a0, s4
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB106_4
; RV64I-NEXT: .LBB106_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -9730,13 +9509,12 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: j .LBB106_1
; RV64I-NEXT: .LBB106_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s4, 16(sp)
-; RV64I-NEXT: ld s3, 24(sp)
-; RV64I-NEXT: ld s2, 32(sp)
-; RV64I-NEXT: ld s1, 40(sp)
-; RV64I-NEXT: ld s0, 48(sp)
-; RV64I-NEXT: ld ra, 56(sp)
-; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: ld s2, 16(sp)
+; RV64I-NEXT: ld s1, 24(sp)
+; RV64I-NEXT: ld s0, 32(sp)
+; RV64I-NEXT: ld ra, 40(sp)
+; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umin_i16_acquire:
@@ -9777,24 +9555,22 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
-; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0
-; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB107_2
; RV32I-NEXT: .LBB107_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1
-; RV32I-NEXT: sh a1, 6(sp)
+; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 3
-; RV32I-NEXT: mv a0, s4
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 6(sp)
+; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB107_4
; RV32I-NEXT: .LBB107_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -9807,7 +9583,6 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: j .LBB107_1
; RV32I-NEXT: .LBB107_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
@@ -9844,30 +9619,28 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i16_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: sd ra, 56(sp)
-; RV64I-NEXT: sd s0, 48(sp)
-; RV64I-NEXT: sd s1, 40(sp)
-; RV64I-NEXT: sd s2, 32(sp)
-; RV64I-NEXT: sd s3, 24(sp)
-; RV64I-NEXT: sd s4, 16(sp)
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp)
+; RV64I-NEXT: sd s0, 32(sp)
+; RV64I-NEXT: sd s1, 24(sp)
+; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0
-; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB107_2
; RV64I-NEXT: .LBB107_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 3
-; RV64I-NEXT: mv a0, s4
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB107_4
; RV64I-NEXT: .LBB107_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -9880,13 +9653,12 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: j .LBB107_1
; RV64I-NEXT: .LBB107_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s4, 16(sp)
-; RV64I-NEXT: ld s3, 24(sp)
-; RV64I-NEXT: ld s2, 32(sp)
-; RV64I-NEXT: ld s1, 40(sp)
-; RV64I-NEXT: ld s0, 48(sp)
-; RV64I-NEXT: ld ra, 56(sp)
-; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: ld s2, 16(sp)
+; RV64I-NEXT: ld s1, 24(sp)
+; RV64I-NEXT: ld s0, 32(sp)
+; RV64I-NEXT: ld ra, 40(sp)
+; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umin_i16_release:
@@ -9927,24 +9699,22 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
-; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0
-; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB108_2
; RV32I-NEXT: .LBB108_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1
-; RV32I-NEXT: sh a1, 6(sp)
+; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2
-; RV32I-NEXT: mv a0, s4
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 6(sp)
+; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB108_4
; RV32I-NEXT: .LBB108_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -9957,7 +9727,6 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: j .LBB108_1
; RV32I-NEXT: .LBB108_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
@@ -9994,30 +9763,28 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i16_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: sd ra, 56(sp)
-; RV64I-NEXT: sd s0, 48(sp)
-; RV64I-NEXT: sd s1, 40(sp)
-; RV64I-NEXT: sd s2, 32(sp)
-; RV64I-NEXT: sd s3, 24(sp)
-; RV64I-NEXT: sd s4, 16(sp)
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp)
+; RV64I-NEXT: sd s0, 32(sp)
+; RV64I-NEXT: sd s1, 24(sp)
+; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0
-; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB108_2
; RV64I-NEXT: .LBB108_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
-; RV64I-NEXT: mv a0, s4
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB108_4
; RV64I-NEXT: .LBB108_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -10030,13 +9797,12 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: j .LBB108_1
; RV64I-NEXT: .LBB108_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s4, 16(sp)
-; RV64I-NEXT: ld s3, 24(sp)
-; RV64I-NEXT: ld s2, 32(sp)
-; RV64I-NEXT: ld s1, 40(sp)
-; RV64I-NEXT: ld s0, 48(sp)
-; RV64I-NEXT: ld ra, 56(sp)
-; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: ld s2, 16(sp)
+; RV64I-NEXT: ld s1, 24(sp)
+; RV64I-NEXT: ld s0, 32(sp)
+; RV64I-NEXT: ld ra, 40(sp)
+; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umin_i16_acq_rel:
@@ -10077,24 +9843,22 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
-; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and s1, s2, s0
-; RV32I-NEXT: addi s3, sp, 6
; RV32I-NEXT: j .LBB109_2
; RV32I-NEXT: .LBB109_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1
-; RV32I-NEXT: sh a1, 6(sp)
+; RV32I-NEXT: sh a1, 10(sp)
+; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5
-; RV32I-NEXT: mv a0, s4
-; RV32I-NEXT: mv a1, s3
+; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 6(sp)
+; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB109_4
; RV32I-NEXT: .LBB109_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -10107,7 +9871,6 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-NEXT: j .LBB109_1
; RV32I-NEXT: .LBB109_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
@@ -10144,30 +9907,28 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i16_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -64
-; RV64I-NEXT: sd ra, 56(sp)
-; RV64I-NEXT: sd s0, 48(sp)
-; RV64I-NEXT: sd s1, 40(sp)
-; RV64I-NEXT: sd s2, 32(sp)
-; RV64I-NEXT: sd s3, 24(sp)
-; RV64I-NEXT: sd s4, 16(sp)
+; RV64I-NEXT: addi sp, sp, -48
+; RV64I-NEXT: sd ra, 40(sp)
+; RV64I-NEXT: sd s0, 32(sp)
+; RV64I-NEXT: sd s1, 24(sp)
+; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s2, a1
-; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and s1, s2, s0
-; RV64I-NEXT: addi s3, sp, 14
; RV64I-NEXT: j .LBB109_2
; RV64I-NEXT: .LBB109_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
-; RV64I-NEXT: mv a0, s4
-; RV64I-NEXT: mv a1, s3
+; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB109_4
; RV64I-NEXT: .LBB109_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -10180,13 +9941,12 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV64I-NEXT: j .LBB109_1
; RV64I-NEXT: .LBB109_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld s4, 16(sp)
-; RV64I-NEXT: ld s3, 24(sp)
-; RV64I-NEXT: ld s2, 32(sp)
-; RV64I-NEXT: ld s1, 40(sp)
-; RV64I-NEXT: ld s0, 48(sp)
-; RV64I-NEXT: ld ra, 56(sp)
-; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ld s3, 8(sp)
+; RV64I-NEXT: ld s2, 16(sp)
+; RV64I-NEXT: ld s1, 24(sp)
+; RV64I-NEXT: ld s0, 32(sp)
+; RV64I-NEXT: ld ra, 40(sp)
+; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umin_i16_seq_cst:
@@ -11491,25 +11251,23 @@ define i32 @atomicrmw_xor_i32_seq_cst(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB145_2
; RV32I-NEXT: .LBB145_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB145_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB145_4
; RV32I-NEXT: .LBB145_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -11521,11 +11279,10 @@ define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB145_1
; RV32I-NEXT: .LBB145_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_max_i32_monotonic:
@@ -11540,22 +11297,20 @@ define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB145_2
; RV64I-NEXT: .LBB145_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB145_4
; RV64I-NEXT: .LBB145_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -11564,11 +11319,10 @@ define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: blt s1, a0, .LBB145_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB145_1
; RV64I-NEXT: .LBB145_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -11587,25 +11341,23 @@ define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_acquire:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB146_2
; RV32I-NEXT: .LBB146_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB146_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB146_4
; RV32I-NEXT: .LBB146_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -11617,11 +11369,10 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB146_1
; RV32I-NEXT: .LBB146_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_max_i32_acquire:
@@ -11636,22 +11387,20 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB146_2
; RV64I-NEXT: .LBB146_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB146_4
; RV64I-NEXT: .LBB146_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -11660,11 +11409,10 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: blt s1, a0, .LBB146_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB146_1
; RV64I-NEXT: .LBB146_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -11683,25 +11431,23 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_release:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB147_2
; RV32I-NEXT: .LBB147_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB147_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB147_4
; RV32I-NEXT: .LBB147_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -11713,11 +11459,10 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB147_1
; RV32I-NEXT: .LBB147_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_max_i32_release:
@@ -11732,22 +11477,20 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB147_2
; RV64I-NEXT: .LBB147_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB147_4
; RV64I-NEXT: .LBB147_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -11756,11 +11499,10 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: blt s1, a0, .LBB147_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB147_1
; RV64I-NEXT: .LBB147_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -11779,25 +11521,23 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_acq_rel:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB148_2
; RV32I-NEXT: .LBB148_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB148_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB148_4
; RV32I-NEXT: .LBB148_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -11809,11 +11549,10 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB148_1
; RV32I-NEXT: .LBB148_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_max_i32_acq_rel:
@@ -11828,22 +11567,20 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB148_2
; RV64I-NEXT: .LBB148_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB148_4
; RV64I-NEXT: .LBB148_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -11852,11 +11589,10 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: blt s1, a0, .LBB148_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB148_1
; RV64I-NEXT: .LBB148_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -11875,25 +11611,23 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i32_seq_cst:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB149_2
; RV32I-NEXT: .LBB149_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB149_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB149_4
; RV32I-NEXT: .LBB149_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -11905,11 +11639,10 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB149_1
; RV32I-NEXT: .LBB149_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_max_i32_seq_cst:
@@ -11924,22 +11657,20 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB149_2
; RV64I-NEXT: .LBB149_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB149_4
; RV64I-NEXT: .LBB149_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -11948,11 +11679,10 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: blt s1, a0, .LBB149_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB149_1
; RV64I-NEXT: .LBB149_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -11971,25 +11701,23 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB150_2
; RV32I-NEXT: .LBB150_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB150_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB150_4
; RV32I-NEXT: .LBB150_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12001,11 +11729,10 @@ define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB150_1
; RV32I-NEXT: .LBB150_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_min_i32_monotonic:
@@ -12020,22 +11747,20 @@ define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB150_2
; RV64I-NEXT: .LBB150_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB150_4
; RV64I-NEXT: .LBB150_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12044,11 +11769,10 @@ define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bge s1, a0, .LBB150_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB150_1
; RV64I-NEXT: .LBB150_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -12067,25 +11791,23 @@ define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_acquire:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB151_2
; RV32I-NEXT: .LBB151_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB151_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB151_4
; RV32I-NEXT: .LBB151_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12097,11 +11819,10 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB151_1
; RV32I-NEXT: .LBB151_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_min_i32_acquire:
@@ -12116,22 +11837,20 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB151_2
; RV64I-NEXT: .LBB151_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB151_4
; RV64I-NEXT: .LBB151_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12140,11 +11859,10 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bge s1, a0, .LBB151_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB151_1
; RV64I-NEXT: .LBB151_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -12163,25 +11881,23 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_release:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB152_2
; RV32I-NEXT: .LBB152_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB152_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB152_4
; RV32I-NEXT: .LBB152_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12193,11 +11909,10 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB152_1
; RV32I-NEXT: .LBB152_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_min_i32_release:
@@ -12212,22 +11927,20 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB152_2
; RV64I-NEXT: .LBB152_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB152_4
; RV64I-NEXT: .LBB152_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12236,11 +11949,10 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bge s1, a0, .LBB152_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB152_1
; RV64I-NEXT: .LBB152_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -12259,25 +11971,23 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_acq_rel:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB153_2
; RV32I-NEXT: .LBB153_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB153_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB153_4
; RV32I-NEXT: .LBB153_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12289,11 +11999,10 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB153_1
; RV32I-NEXT: .LBB153_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_min_i32_acq_rel:
@@ -12308,22 +12017,20 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB153_2
; RV64I-NEXT: .LBB153_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB153_4
; RV64I-NEXT: .LBB153_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12332,11 +12039,10 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bge s1, a0, .LBB153_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB153_1
; RV64I-NEXT: .LBB153_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -12355,25 +12061,23 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i32_seq_cst:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB154_2
; RV32I-NEXT: .LBB154_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB154_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB154_4
; RV32I-NEXT: .LBB154_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12385,11 +12089,10 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB154_1
; RV32I-NEXT: .LBB154_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_min_i32_seq_cst:
@@ -12404,22 +12107,20 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB154_2
; RV64I-NEXT: .LBB154_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB154_4
; RV64I-NEXT: .LBB154_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12428,11 +12129,10 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bge s1, a0, .LBB154_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB154_1
; RV64I-NEXT: .LBB154_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -12451,25 +12151,23 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB155_2
; RV32I-NEXT: .LBB155_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB155_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB155_4
; RV32I-NEXT: .LBB155_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12481,11 +12179,10 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB155_1
; RV32I-NEXT: .LBB155_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_umax_i32_monotonic:
@@ -12500,22 +12197,20 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB155_2
; RV64I-NEXT: .LBB155_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB155_4
; RV64I-NEXT: .LBB155_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12524,11 +12219,10 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bltu s1, a0, .LBB155_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB155_1
; RV64I-NEXT: .LBB155_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -12547,25 +12241,23 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_acquire:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB156_2
; RV32I-NEXT: .LBB156_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB156_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB156_4
; RV32I-NEXT: .LBB156_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12577,11 +12269,10 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB156_1
; RV32I-NEXT: .LBB156_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_umax_i32_acquire:
@@ -12596,22 +12287,20 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB156_2
; RV64I-NEXT: .LBB156_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB156_4
; RV64I-NEXT: .LBB156_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12620,11 +12309,10 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bltu s1, a0, .LBB156_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB156_1
; RV64I-NEXT: .LBB156_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -12643,25 +12331,23 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_release:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB157_2
; RV32I-NEXT: .LBB157_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB157_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB157_4
; RV32I-NEXT: .LBB157_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12673,11 +12359,10 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB157_1
; RV32I-NEXT: .LBB157_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_umax_i32_release:
@@ -12692,22 +12377,20 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB157_2
; RV64I-NEXT: .LBB157_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB157_4
; RV64I-NEXT: .LBB157_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12716,11 +12399,10 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bltu s1, a0, .LBB157_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB157_1
; RV64I-NEXT: .LBB157_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -12739,25 +12421,23 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_acq_rel:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB158_2
; RV32I-NEXT: .LBB158_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB158_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB158_4
; RV32I-NEXT: .LBB158_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12769,11 +12449,10 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB158_1
; RV32I-NEXT: .LBB158_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_umax_i32_acq_rel:
@@ -12788,22 +12467,20 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB158_2
; RV64I-NEXT: .LBB158_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB158_4
; RV64I-NEXT: .LBB158_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12812,11 +12489,10 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bltu s1, a0, .LBB158_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB158_1
; RV64I-NEXT: .LBB158_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -12835,25 +12511,23 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i32_seq_cst:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB159_2
; RV32I-NEXT: .LBB159_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB159_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB159_4
; RV32I-NEXT: .LBB159_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12865,11 +12539,10 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB159_1
; RV32I-NEXT: .LBB159_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_umax_i32_seq_cst:
@@ -12884,22 +12557,20 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB159_2
; RV64I-NEXT: .LBB159_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB159_4
; RV64I-NEXT: .LBB159_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12908,11 +12579,10 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bltu s1, a0, .LBB159_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB159_1
; RV64I-NEXT: .LBB159_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -12931,25 +12601,23 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB160_2
; RV32I-NEXT: .LBB160_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB160_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB160_4
; RV32I-NEXT: .LBB160_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -12961,11 +12629,10 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB160_1
; RV32I-NEXT: .LBB160_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_umin_i32_monotonic:
@@ -12980,22 +12647,20 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB160_2
; RV64I-NEXT: .LBB160_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB160_4
; RV64I-NEXT: .LBB160_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -13004,11 +12669,10 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bgeu s1, a0, .LBB160_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB160_1
; RV64I-NEXT: .LBB160_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -13027,25 +12691,23 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_acquire:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB161_2
; RV32I-NEXT: .LBB161_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB161_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB161_4
; RV32I-NEXT: .LBB161_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -13057,11 +12719,10 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB161_1
; RV32I-NEXT: .LBB161_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_umin_i32_acquire:
@@ -13076,22 +12737,20 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB161_2
; RV64I-NEXT: .LBB161_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB161_4
; RV64I-NEXT: .LBB161_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -13100,11 +12759,10 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bgeu s1, a0, .LBB161_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB161_1
; RV64I-NEXT: .LBB161_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -13123,27 +12781,25 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_release:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB162_2
; RV32I-NEXT: .LBB162_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB162_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB162_4
-; RV32I-NEXT: LBB162_2: # %atomicrmw.start
+; RV32I-NEXT: .LBB162_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a3, .LBB162_1
@@ -13153,11 +12809,10 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB162_1
; RV32I-NEXT: .LBB162_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_umin_i32_release:
@@ -13172,22 +12827,20 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB162_2
; RV64I-NEXT: .LBB162_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB162_4
; RV64I-NEXT: .LBB162_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -13196,11 +12849,10 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bgeu s1, a0, .LBB162_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB162_1
; RV64I-NEXT: .LBB162_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -13219,25 +12871,23 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind {
define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i32_acq_rel:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB163_2
; RV32I-NEXT: .LBB163_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB163_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 4
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB163_4
; RV32I-NEXT: .LBB163_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -13249,11 +12899,10 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB163_1
; RV32I-NEXT: .LBB163_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_umin_i32_acq_rel:
@@ -13268,22 +12917,20 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB163_2
; RV64I-NEXT: .LBB163_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB163_4
; RV64I-NEXT: .LBB163_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -13292,11 +12939,10 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bgeu s1, a0, .LBB163_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB163_1
; RV64I-NEXT: .LBB163_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -13312,28 +12958,26 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind {
ret i32 %1
}
-define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
-; RV32I-LABEL: atomicrmw_umin_i32_seq_cst:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: sw s0, 24(sp)
-; RV32I-NEXT: sw s1, 20(sp)
-; RV32I-NEXT: sw s2, 16(sp)
+define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
+; RV32I-LABEL: atomicrmw_umin_i32_seq_cst:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp)
+; RV32I-NEXT: sw s0, 8(sp)
+; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: mv s1, a1
-; RV32I-NEXT: addi s2, sp, 12
; RV32I-NEXT: j .LBB164_2
; RV32I-NEXT: .LBB164_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB164_2 Depth=1
-; RV32I-NEXT: sw a3, 12(sp)
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: lw a3, 0(sp)
; RV32I-NEXT: bnez a0, .LBB164_4
; RV32I-NEXT: .LBB164_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -13345,11 +12989,10 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV32I-NEXT: j .LBB164_1
; RV32I-NEXT: .LBB164_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: lw s2, 16(sp)
-; RV32I-NEXT: lw s1, 20(sp)
-; RV32I-NEXT: lw s0, 24(sp)
-; RV32I-NEXT: lw ra, 28(sp)
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw s1, 4(sp)
+; RV32I-NEXT: lw s0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp)
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_umin_i32_seq_cst:
@@ -13364,22 +13007,20 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp)
-; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lwu a3, 0(a0)
-; RV64I-NEXT: mv s3, a1
+; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: sext.w s1, a1
-; RV64I-NEXT: addi s2, sp, 4
; RV64I-NEXT: j .LBB164_2
; RV64I-NEXT: .LBB164_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1
-; RV64I-NEXT: sw a3, 4(sp)
+; RV64I-NEXT: sw a3, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a3, 4(sp)
+; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB164_4
; RV64I-NEXT: .LBB164_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -13388,11 +13029,10 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
; RV64I-NEXT: bgeu s1, a0, .LBB164_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1
-; RV64I-NEXT: mv a2, s3
+; RV64I-NEXT: mv a2, s2
; RV64I-NEXT: j .LBB164_1
; RV64I-NEXT: .LBB164_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp)
@@ -14821,25 +14461,23 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB200_2
; RV32I-NEXT: .LBB200_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB200_7
; RV32I-NEXT: .LBB200_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -14848,7 +14486,7 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB200_5
-; RV32I-NEXT: .LBB200_4:
+; RV32I-NEXT: .LBB200_4: # in Loop: Header=BB200_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB200_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB200_2 Depth=1
@@ -14863,7 +14501,6 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB200_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -14878,25 +14515,23 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB200_2
; RV32IA-NEXT: .LBB200_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB200_7
; RV32IA-NEXT: .LBB200_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -14905,7 +14540,7 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB200_5
-; RV32IA-NEXT: .LBB200_4:
+; RV32IA-NEXT: .LBB200_4: # in Loop: Header=BB200_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB200_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB200_2 Depth=1
@@ -14920,7 +14555,6 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB200_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -14930,25 +14564,23 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i64_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB200_2
; RV64I-NEXT: .LBB200_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB200_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB200_4
; RV64I-NEXT: .LBB200_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -14960,11 +14592,10 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB200_1
; RV64I-NEXT: .LBB200_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_max_i64_monotonic:
@@ -14983,25 +14614,23 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB201_2
; RV32I-NEXT: .LBB201_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB201_7
; RV32I-NEXT: .LBB201_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15010,7 +14639,7 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB201_5
-; RV32I-NEXT: .LBB201_4:
+; RV32I-NEXT: .LBB201_4: # in Loop: Header=BB201_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB201_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB201_2 Depth=1
@@ -15025,7 +14654,6 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB201_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -15040,25 +14668,23 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB201_2
; RV32IA-NEXT: .LBB201_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB201_7
; RV32IA-NEXT: .LBB201_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15067,7 +14693,7 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB201_5
-; RV32IA-NEXT: .LBB201_4:
+; RV32IA-NEXT: .LBB201_4: # in Loop: Header=BB201_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB201_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB201_2 Depth=1
@@ -15082,7 +14708,6 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB201_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -15092,25 +14717,23 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i64_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB201_2
; RV64I-NEXT: .LBB201_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB201_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB201_4
; RV64I-NEXT: .LBB201_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15122,11 +14745,10 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB201_1
; RV64I-NEXT: .LBB201_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_max_i64_acquire:
@@ -15145,25 +14767,23 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB202_2
; RV32I-NEXT: .LBB202_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB202_7
; RV32I-NEXT: .LBB202_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15172,7 +14792,7 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB202_5
-; RV32I-NEXT: .LBB202_4:
+; RV32I-NEXT: .LBB202_4: # in Loop: Header=BB202_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB202_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB202_2 Depth=1
@@ -15187,7 +14807,6 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB202_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -15202,25 +14821,23 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB202_2
; RV32IA-NEXT: .LBB202_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB202_7
; RV32IA-NEXT: .LBB202_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15229,7 +14846,7 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB202_5
-; RV32IA-NEXT: .LBB202_4:
+; RV32IA-NEXT: .LBB202_4: # in Loop: Header=BB202_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB202_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB202_2 Depth=1
@@ -15244,7 +14861,6 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB202_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -15254,25 +14870,23 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i64_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB202_2
; RV64I-NEXT: .LBB202_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB202_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB202_4
; RV64I-NEXT: .LBB202_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15284,11 +14898,10 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB202_1
; RV64I-NEXT: .LBB202_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_max_i64_release:
@@ -15307,25 +14920,23 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB203_2
; RV32I-NEXT: .LBB203_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB203_7
; RV32I-NEXT: .LBB203_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15334,7 +14945,7 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB203_5
-; RV32I-NEXT: .LBB203_4:
+; RV32I-NEXT: .LBB203_4: # in Loop: Header=BB203_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB203_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB203_2 Depth=1
@@ -15349,7 +14960,6 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB203_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -15364,25 +14974,23 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB203_2
; RV32IA-NEXT: .LBB203_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB203_7
; RV32IA-NEXT: .LBB203_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15391,7 +14999,7 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB203_5
-; RV32IA-NEXT: .LBB203_4:
+; RV32IA-NEXT: .LBB203_4: # in Loop: Header=BB203_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB203_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB203_2 Depth=1
@@ -15406,7 +15014,6 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB203_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -15416,25 +15023,23 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i64_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB203_2
; RV64I-NEXT: .LBB203_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB203_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB203_4
; RV64I-NEXT: .LBB203_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15446,11 +15051,10 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB203_1
; RV64I-NEXT: .LBB203_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_max_i64_acq_rel:
@@ -15469,25 +15073,23 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB204_2
; RV32I-NEXT: .LBB204_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB204_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB204_7
; RV32I-NEXT: .LBB204_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15496,7 +15098,7 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB204_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB204_5
-; RV32I-NEXT: .LBB204_4:
+; RV32I-NEXT: .LBB204_4: # in Loop: Header=BB204_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB204_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB204_2 Depth=1
@@ -15511,7 +15113,6 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB204_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -15526,25 +15127,23 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB204_2
; RV32IA-NEXT: .LBB204_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB204_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB204_7
; RV32IA-NEXT: .LBB204_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15553,7 +15152,7 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB204_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB204_5
-; RV32IA-NEXT: .LBB204_4:
+; RV32IA-NEXT: .LBB204_4: # in Loop: Header=BB204_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB204_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB204_2 Depth=1
@@ -15568,7 +15167,6 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB204_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -15578,25 +15176,23 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i64_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB204_2
; RV64I-NEXT: .LBB204_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB204_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB204_4
; RV64I-NEXT: .LBB204_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15608,11 +15204,10 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB204_1
; RV64I-NEXT: .LBB204_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_max_i64_seq_cst:
@@ -15631,25 +15226,23 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB205_2
; RV32I-NEXT: .LBB205_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB205_7
; RV32I-NEXT: .LBB205_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15658,7 +15251,7 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB205_5
-; RV32I-NEXT: .LBB205_4:
+; RV32I-NEXT: .LBB205_4: # in Loop: Header=BB205_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB205_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1
@@ -15674,7 +15267,6 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB205_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -15689,25 +15281,23 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB205_2
; RV32IA-NEXT: .LBB205_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB205_7
; RV32IA-NEXT: .LBB205_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15716,7 +15306,7 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB205_5
-; RV32IA-NEXT: .LBB205_4:
+; RV32IA-NEXT: .LBB205_4: # in Loop: Header=BB205_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB205_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1
@@ -15732,7 +15322,6 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB205_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -15742,25 +15331,23 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i64_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB205_2
; RV64I-NEXT: .LBB205_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB205_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB205_4
; RV64I-NEXT: .LBB205_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15772,11 +15359,10 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB205_1
; RV64I-NEXT: .LBB205_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_min_i64_monotonic:
@@ -15795,25 +15381,23 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB206_2
; RV32I-NEXT: .LBB206_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB206_7
; RV32I-NEXT: .LBB206_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15822,7 +15406,7 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB206_5
-; RV32I-NEXT: .LBB206_4:
+; RV32I-NEXT: .LBB206_4: # in Loop: Header=BB206_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB206_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1
@@ -15838,7 +15422,6 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB206_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -15853,25 +15436,23 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB206_2
; RV32IA-NEXT: .LBB206_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB206_7
; RV32IA-NEXT: .LBB206_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15880,7 +15461,7 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB206_5
-; RV32IA-NEXT: .LBB206_4:
+; RV32IA-NEXT: .LBB206_4: # in Loop: Header=BB206_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB206_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1
@@ -15896,7 +15477,6 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB206_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -15906,25 +15486,23 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i64_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB206_2
; RV64I-NEXT: .LBB206_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB206_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB206_4
; RV64I-NEXT: .LBB206_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15936,11 +15514,10 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB206_1
; RV64I-NEXT: .LBB206_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_min_i64_acquire:
@@ -15959,25 +15536,23 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB207_2
; RV32I-NEXT: .LBB207_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB207_7
; RV32I-NEXT: .LBB207_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -15986,7 +15561,7 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB207_5
-; RV32I-NEXT: .LBB207_4:
+; RV32I-NEXT: .LBB207_4: # in Loop: Header=BB207_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB207_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1
@@ -16002,7 +15577,6 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB207_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -16017,25 +15591,23 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB207_2
; RV32IA-NEXT: .LBB207_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB207_7
; RV32IA-NEXT: .LBB207_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16044,7 +15616,7 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB207_5
-; RV32IA-NEXT: .LBB207_4:
+; RV32IA-NEXT: .LBB207_4: # in Loop: Header=BB207_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB207_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1
@@ -16060,7 +15632,6 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB207_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -16070,25 +15641,23 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i64_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB207_2
; RV64I-NEXT: .LBB207_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB207_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB207_4
; RV64I-NEXT: .LBB207_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16100,11 +15669,10 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB207_1
; RV64I-NEXT: .LBB207_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_min_i64_release:
@@ -16123,25 +15691,23 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB208_2
; RV32I-NEXT: .LBB208_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB208_7
; RV32I-NEXT: .LBB208_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16150,7 +15716,7 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB208_5
-; RV32I-NEXT: .LBB208_4:
+; RV32I-NEXT: .LBB208_4: # in Loop: Header=BB208_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB208_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1
@@ -16166,7 +15732,6 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB208_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -16181,25 +15746,23 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB208_2
; RV32IA-NEXT: .LBB208_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB208_7
; RV32IA-NEXT: .LBB208_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16208,7 +15771,7 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB208_5
-; RV32IA-NEXT: .LBB208_4:
+; RV32IA-NEXT: .LBB208_4: # in Loop: Header=BB208_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB208_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1
@@ -16224,7 +15787,6 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB208_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -16234,25 +15796,23 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i64_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB208_2
; RV64I-NEXT: .LBB208_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB208_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB208_4
; RV64I-NEXT: .LBB208_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16264,11 +15824,10 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB208_1
; RV64I-NEXT: .LBB208_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_min_i64_acq_rel:
@@ -16287,25 +15846,23 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB209_2
; RV32I-NEXT: .LBB209_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB209_7
; RV32I-NEXT: .LBB209_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16314,7 +15871,7 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV32I-NEXT: slt a0, s1, a5
; RV32I-NEXT: j .LBB209_5
-; RV32I-NEXT: .LBB209_4:
+; RV32I-NEXT: .LBB209_4: # in Loop: Header=BB209_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB209_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1
@@ -16330,7 +15887,6 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB209_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -16345,25 +15901,23 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB209_2
; RV32IA-NEXT: .LBB209_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB209_7
; RV32IA-NEXT: .LBB209_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16372,7 +15926,7 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV32IA-NEXT: slt a0, s1, a5
; RV32IA-NEXT: j .LBB209_5
-; RV32IA-NEXT: .LBB209_4:
+; RV32IA-NEXT: .LBB209_4: # in Loop: Header=BB209_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB209_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1
@@ -16388,7 +15942,6 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB209_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -16398,25 +15951,23 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i64_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB209_2
; RV64I-NEXT: .LBB209_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB209_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB209_4
; RV64I-NEXT: .LBB209_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16428,11 +15979,10 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB209_1
; RV64I-NEXT: .LBB209_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_min_i64_seq_cst:
@@ -16451,25 +16001,23 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB210_2
; RV32I-NEXT: .LBB210_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB210_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB210_7
; RV32I-NEXT: .LBB210_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16478,7 +16026,7 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB210_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB210_5
-; RV32I-NEXT: .LBB210_4:
+; RV32I-NEXT: .LBB210_4: # in Loop: Header=BB210_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB210_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB210_2 Depth=1
@@ -16493,7 +16041,6 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB210_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -16508,25 +16055,23 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB210_2
; RV32IA-NEXT: .LBB210_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB210_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB210_7
; RV32IA-NEXT: .LBB210_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16535,7 +16080,7 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB210_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB210_5
-; RV32IA-NEXT: .LBB210_4:
+; RV32IA-NEXT: .LBB210_4: # in Loop: Header=BB210_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB210_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB210_2 Depth=1
@@ -16550,7 +16095,6 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB210_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -16560,25 +16104,23 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i64_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB210_2
; RV64I-NEXT: .LBB210_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB210_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB210_4
; RV64I-NEXT: .LBB210_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16590,11 +16132,10 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB210_1
; RV64I-NEXT: .LBB210_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umax_i64_monotonic:
@@ -16613,25 +16154,23 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB211_2
; RV32I-NEXT: .LBB211_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB211_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB211_7
; RV32I-NEXT: .LBB211_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16640,7 +16179,7 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB211_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB211_5
-; RV32I-NEXT: .LBB211_4:
+; RV32I-NEXT: .LBB211_4: # in Loop: Header=BB211_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB211_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB211_2 Depth=1
@@ -16655,7 +16194,6 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB211_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -16670,25 +16208,23 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB211_2
; RV32IA-NEXT: .LBB211_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB211_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB211_7
; RV32IA-NEXT: .LBB211_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16697,7 +16233,7 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB211_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB211_5
-; RV32IA-NEXT: .LBB211_4:
+; RV32IA-NEXT: .LBB211_4: # in Loop: Header=BB211_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB211_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB211_2 Depth=1
@@ -16712,7 +16248,6 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB211_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -16722,25 +16257,23 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i64_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB211_2
; RV64I-NEXT: .LBB211_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB211_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB211_4
; RV64I-NEXT: .LBB211_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16752,11 +16285,10 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB211_1
; RV64I-NEXT: .LBB211_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umax_i64_acquire:
@@ -16775,25 +16307,23 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB212_2
; RV32I-NEXT: .LBB212_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB212_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB212_7
; RV32I-NEXT: .LBB212_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16802,7 +16332,7 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB212_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB212_5
-; RV32I-NEXT: .LBB212_4:
+; RV32I-NEXT: .LBB212_4: # in Loop: Header=BB212_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB212_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB212_2 Depth=1
@@ -16817,7 +16347,6 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB212_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -16832,25 +16361,23 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB212_2
; RV32IA-NEXT: .LBB212_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB212_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB212_7
; RV32IA-NEXT: .LBB212_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16859,7 +16386,7 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB212_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB212_5
-; RV32IA-NEXT: .LBB212_4:
+; RV32IA-NEXT: .LBB212_4: # in Loop: Header=BB212_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB212_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB212_2 Depth=1
@@ -16874,7 +16401,6 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB212_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -16884,25 +16410,23 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i64_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB212_2
; RV64I-NEXT: .LBB212_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB212_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB212_4
; RV64I-NEXT: .LBB212_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16914,11 +16438,10 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB212_1
; RV64I-NEXT: .LBB212_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umax_i64_release:
@@ -16937,25 +16460,23 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB213_2
; RV32I-NEXT: .LBB213_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB213_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB213_7
; RV32I-NEXT: .LBB213_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -16964,7 +16485,7 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB213_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB213_5
-; RV32I-NEXT: .LBB213_4:
+; RV32I-NEXT: .LBB213_4: # in Loop: Header=BB213_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB213_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB213_2 Depth=1
@@ -16979,7 +16500,6 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB213_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -16994,25 +16514,23 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB213_2
; RV32IA-NEXT: .LBB213_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB213_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB213_7
; RV32IA-NEXT: .LBB213_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17021,7 +16539,7 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB213_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB213_5
-; RV32IA-NEXT: .LBB213_4:
+; RV32IA-NEXT: .LBB213_4: # in Loop: Header=BB213_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB213_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB213_2 Depth=1
@@ -17036,7 +16554,6 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB213_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -17046,25 +16563,23 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i64_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB213_2
; RV64I-NEXT: .LBB213_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB213_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB213_4
; RV64I-NEXT: .LBB213_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17076,11 +16591,10 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB213_1
; RV64I-NEXT: .LBB213_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umax_i64_acq_rel:
@@ -17099,25 +16613,23 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB214_2
; RV32I-NEXT: .LBB214_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB214_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB214_7
; RV32I-NEXT: .LBB214_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17126,7 +16638,7 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB214_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB214_5
-; RV32I-NEXT: .LBB214_4:
+; RV32I-NEXT: .LBB214_4: # in Loop: Header=BB214_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB214_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB214_2 Depth=1
@@ -17141,7 +16653,6 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB214_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -17156,25 +16667,23 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB214_2
; RV32IA-NEXT: .LBB214_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB214_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB214_7
; RV32IA-NEXT: .LBB214_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17183,7 +16692,7 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB214_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB214_5
-; RV32IA-NEXT: .LBB214_4:
+; RV32IA-NEXT: .LBB214_4: # in Loop: Header=BB214_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB214_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB214_2 Depth=1
@@ -17198,7 +16707,6 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB214_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -17208,25 +16716,23 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i64_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB214_2
; RV64I-NEXT: .LBB214_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB214_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB214_4
; RV64I-NEXT: .LBB214_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17238,11 +16744,10 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB214_1
; RV64I-NEXT: .LBB214_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umax_i64_seq_cst:
@@ -17261,25 +16766,23 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB215_2
; RV32I-NEXT: .LBB215_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a4, zero
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB215_7
; RV32I-NEXT: .LBB215_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17288,7 +16791,7 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB215_5
-; RV32I-NEXT: .LBB215_4:
+; RV32I-NEXT: .LBB215_4: # in Loop: Header=BB215_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB215_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1
@@ -17304,7 +16807,6 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB215_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -17319,25 +16821,23 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB215_2
; RV32IA-NEXT: .LBB215_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a4, zero
; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB215_7
; RV32IA-NEXT: .LBB215_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17346,7 +16846,7 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB215_5
-; RV32IA-NEXT: .LBB215_4:
+; RV32IA-NEXT: .LBB215_4: # in Loop: Header=BB215_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB215_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1
@@ -17362,7 +16862,6 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB215_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -17372,25 +16871,23 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i64_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB215_2
; RV64I-NEXT: .LBB215_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB215_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB215_4
; RV64I-NEXT: .LBB215_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17402,11 +16899,10 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB215_1
; RV64I-NEXT: .LBB215_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umin_i64_monotonic:
@@ -17425,25 +16921,23 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB216_2
; RV32I-NEXT: .LBB216_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB216_7
; RV32I-NEXT: .LBB216_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17452,7 +16946,7 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB216_5
-; RV32I-NEXT: .LBB216_4:
+; RV32I-NEXT: .LBB216_4: # in Loop: Header=BB216_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB216_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1
@@ -17468,7 +16962,6 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB216_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -17483,25 +16976,23 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB216_2
; RV32IA-NEXT: .LBB216_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB216_7
; RV32IA-NEXT: .LBB216_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17510,7 +17001,7 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB216_5
-; RV32IA-NEXT: .LBB216_4:
+; RV32IA-NEXT: .LBB216_4: # in Loop: Header=BB216_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB216_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1
@@ -17526,7 +17017,6 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB216_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -17536,25 +17026,23 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i64_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB216_2
; RV64I-NEXT: .LBB216_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB216_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB216_4
; RV64I-NEXT: .LBB216_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17566,11 +17054,10 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB216_1
; RV64I-NEXT: .LBB216_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umin_i64_acquire:
@@ -17589,25 +17076,23 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB217_2
; RV32I-NEXT: .LBB217_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB217_7
; RV32I-NEXT: .LBB217_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17616,7 +17101,7 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB217_5
-; RV32I-NEXT: .LBB217_4:
+; RV32I-NEXT: .LBB217_4: # in Loop: Header=BB217_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB217_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1
@@ -17632,7 +17117,6 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB217_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -17647,25 +17131,23 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB217_2
; RV32IA-NEXT: .LBB217_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB217_7
; RV32IA-NEXT: .LBB217_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17674,7 +17156,7 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB217_5
-; RV32IA-NEXT: .LBB217_4:
+; RV32IA-NEXT: .LBB217_4: # in Loop: Header=BB217_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB217_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1
@@ -17690,7 +17172,6 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB217_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -17700,25 +17181,23 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i64_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB217_2
; RV64I-NEXT: .LBB217_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB217_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 3
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB217_4
; RV64I-NEXT: .LBB217_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17730,11 +17209,10 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB217_1
; RV64I-NEXT: .LBB217_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umin_i64_release:
@@ -17753,25 +17231,23 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB218_2
; RV32I-NEXT: .LBB218_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB218_7
; RV32I-NEXT: .LBB218_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17780,7 +17256,7 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB218_5
-; RV32I-NEXT: .LBB218_4:
+; RV32I-NEXT: .LBB218_4: # in Loop: Header=BB218_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB218_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1
@@ -17796,7 +17272,6 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB218_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -17811,25 +17286,23 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB218_2
; RV32IA-NEXT: .LBB218_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB218_7
; RV32IA-NEXT: .LBB218_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17838,7 +17311,7 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB218_5
-; RV32IA-NEXT: .LBB218_4:
+; RV32IA-NEXT: .LBB218_4: # in Loop: Header=BB218_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB218_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1
@@ -17854,7 +17327,6 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB218_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -17864,25 +17336,23 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i64_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB218_2
; RV64I-NEXT: .LBB218_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB218_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB218_4
; RV64I-NEXT: .LBB218_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17894,11 +17364,10 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB218_1
; RV64I-NEXT: .LBB218_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umin_i64_acq_rel:
@@ -17917,25 +17386,23 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
-; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
-; RV32I-NEXT: mv s3, sp
; RV32I-NEXT: j .LBB219_2
; RV32I-NEXT: .LBB219_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1
-; RV32I-NEXT: sw a4, 0(sp)
-; RV32I-NEXT: sw a5, 4(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a5, 12(sp)
+; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a0, s0
-; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __atomic_compare_exchange_8
-; RV32I-NEXT: lw a5, 4(sp)
-; RV32I-NEXT: lw a4, 0(sp)
+; RV32I-NEXT: lw a5, 12(sp)
+; RV32I-NEXT: lw a4, 8(sp)
; RV32I-NEXT: bnez a0, .LBB219_7
; RV32I-NEXT: .LBB219_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -17944,7 +17411,7 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV32I-NEXT: sltu a0, s1, a5
; RV32I-NEXT: j .LBB219_5
-; RV32I-NEXT: .LBB219_4:
+; RV32I-NEXT: .LBB219_4: # in Loop: Header=BB219_2 Depth=1
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB219_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1
@@ -17960,7 +17427,6 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32I-NEXT: .LBB219_7: # %atomicrmw.end
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
-; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
@@ -17975,25 +17441,23 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: sw s0, 24(sp)
; RV32IA-NEXT: sw s1, 20(sp)
; RV32IA-NEXT: sw s2, 16(sp)
-; RV32IA-NEXT: sw s3, 12(sp)
; RV32IA-NEXT: mv s0, a0
; RV32IA-NEXT: lw a5, 4(a0)
; RV32IA-NEXT: lw a4, 0(a0)
; RV32IA-NEXT: mv s1, a2
; RV32IA-NEXT: mv s2, a1
-; RV32IA-NEXT: mv s3, sp
; RV32IA-NEXT: j .LBB219_2
; RV32IA-NEXT: .LBB219_1: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1
-; RV32IA-NEXT: sw a4, 0(sp)
-; RV32IA-NEXT: sw a5, 4(sp)
+; RV32IA-NEXT: sw a4, 8(sp)
+; RV32IA-NEXT: sw a5, 12(sp)
+; RV32IA-NEXT: addi a1, sp, 8
; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a0, s0
-; RV32IA-NEXT: mv a1, s3
; RV32IA-NEXT: call __atomic_compare_exchange_8
-; RV32IA-NEXT: lw a5, 4(sp)
-; RV32IA-NEXT: lw a4, 0(sp)
+; RV32IA-NEXT: lw a5, 12(sp)
+; RV32IA-NEXT: lw a4, 8(sp)
; RV32IA-NEXT: bnez a0, .LBB219_7
; RV32IA-NEXT: .LBB219_2: # %atomicrmw.start
; RV32IA-NEXT: # =>This Inner Loop Header: Depth=1
@@ -18002,7 +17466,7 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV32IA-NEXT: sltu a0, s1, a5
; RV32IA-NEXT: j .LBB219_5
-; RV32IA-NEXT: .LBB219_4:
+; RV32IA-NEXT: .LBB219_4: # in Loop: Header=BB219_2 Depth=1
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB219_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1
@@ -18018,7 +17482,6 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV32IA-NEXT: .LBB219_7: # %atomicrmw.end
; RV32IA-NEXT: mv a0, a4
; RV32IA-NEXT: mv a1, a5
-; RV32IA-NEXT: lw s3, 12(sp)
; RV32IA-NEXT: lw s2, 16(sp)
; RV32IA-NEXT: lw s1, 20(sp)
; RV32IA-NEXT: lw s0, 24(sp)
@@ -18028,25 +17491,23 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i64_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp)
-; RV64I-NEXT: sd s0, 32(sp)
-; RV64I-NEXT: sd s1, 24(sp)
-; RV64I-NEXT: sd s2, 16(sp)
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp)
+; RV64I-NEXT: sd s0, 16(sp)
+; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: mv s1, a1
-; RV64I-NEXT: addi s2, sp, 8
; RV64I-NEXT: j .LBB219_2
; RV64I-NEXT: .LBB219_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB219_2 Depth=1
-; RV64I-NEXT: sd a3, 8(sp)
+; RV64I-NEXT: sd a3, 0(sp)
+; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: mv a0, s0
-; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __atomic_compare_exchange_8
-; RV64I-NEXT: ld a3, 8(sp)
+; RV64I-NEXT: ld a3, 0(sp)
; RV64I-NEXT: bnez a0, .LBB219_4
; RV64I-NEXT: .LBB219_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
@@ -18058,11 +17519,10 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind {
; RV64I-NEXT: j .LBB219_1
; RV64I-NEXT: .LBB219_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: ld s2, 16(sp)
-; RV64I-NEXT: ld s1, 24(sp)
-; RV64I-NEXT: ld s0, 32(sp)
-; RV64I-NEXT: ld ra, 40(sp)
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld s1, 8(sp)
+; RV64I-NEXT: ld s0, 16(sp)
+; RV64I-NEXT: ld ra, 24(sp)
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umin_i64_seq_cst:
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
index 24788e110b46..284476fffe05 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
@@ -172,9 +172,9 @@ define void @caller_aligned_stack() nounwind {
; RV32I-FPELIM-NEXT: addi t0, a0, 1311
; RV32I-FPELIM-NEXT: lui a0, 688509
; RV32I-FPELIM-NEXT: addi a5, a0, -2048
-; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 11
+; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a3, zero, 12
; RV32I-FPELIM-NEXT: addi a4, zero, 13
; RV32I-FPELIM-NEXT: addi a6, zero, 4
@@ -218,9 +218,9 @@ define void @caller_aligned_stack() nounwind {
; RV32I-WITHFP-NEXT: addi t0, a0, 1311
; RV32I-WITHFP-NEXT: lui a0, 688509
; RV32I-WITHFP-NEXT: addi a5, a0, -2048
-; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 11
+; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a3, zero, 12
; RV32I-WITHFP-NEXT: addi a4, zero, 13
; RV32I-WITHFP-NEXT: addi a6, zero, 4
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
index e86a8c7406f7..3e7945887f4d 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
@@ -368,7 +368,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-FPELIM-NEXT: sw zero, 48(sp)
; RV32I-FPELIM-NEXT: sw zero, 44(sp)
; RV32I-FPELIM-NEXT: addi t0, zero, 8
-; RV32I-FPELIM-NEXT: addi a7, sp, 40
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: addi a2, zero, 3
@@ -376,6 +375,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-FPELIM-NEXT: addi a4, zero, 5
; RV32I-FPELIM-NEXT: addi a5, zero, 6
; RV32I-FPELIM-NEXT: addi a6, zero, 7
+; RV32I-FPELIM-NEXT: addi a7, sp, 40
; RV32I-FPELIM-NEXT: sw t0, 40(sp)
; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs
; RV32I-FPELIM-NEXT: lw ra, 60(sp)
@@ -401,7 +401,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-WITHFP-NEXT: sw zero, -16(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: addi t0, zero, 8
-; RV32I-WITHFP-NEXT: addi a7, s0, -24
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: addi a2, zero, 3
@@ -409,6 +408,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-WITHFP-NEXT: addi a4, zero, 5
; RV32I-WITHFP-NEXT: addi a5, zero, 6
; RV32I-WITHFP-NEXT: addi a6, zero, 7
+; RV32I-WITHFP-NEXT: addi a7, s0, -24
; RV32I-WITHFP-NEXT: sw t0, -24(s0)
; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs
; RV32I-WITHFP-NEXT: lw s0, 56(sp)
@@ -693,9 +693,9 @@ define void @caller_aligned_stack() nounwind {
; RV32I-FPELIM-NEXT: addi t0, a0, 1311
; RV32I-FPELIM-NEXT: lui a0, 688509
; RV32I-FPELIM-NEXT: addi a5, a0, -2048
-; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 11
+; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a3, zero, 12
; RV32I-FPELIM-NEXT: addi a4, zero, 13
; RV32I-FPELIM-NEXT: addi a6, zero, 4
@@ -736,9 +736,9 @@ define void @caller_aligned_stack() nounwind {
; RV32I-WITHFP-NEXT: addi t0, a0, 1311
; RV32I-WITHFP-NEXT: lui a0, 688509
; RV32I-WITHFP-NEXT: addi a5, a0, -2048
-; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 11
+; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a3, zero, 12
; RV32I-WITHFP-NEXT: addi a4, zero, 13
; RV32I-WITHFP-NEXT: addi a6, zero, 4
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
index 95cf39e79d3c..fac227f4978c 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
@@ -202,7 +202,6 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
; RV64I-NEXT: sd zero, 64(sp)
; RV64I-NEXT: sd zero, 56(sp)
; RV64I-NEXT: addi t0, zero, 8
-; RV64I-NEXT: addi a7, sp, 48
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: addi a2, zero, 3
@@ -210,6 +209,7 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: addi a5, zero, 6
; RV64I-NEXT: addi a6, zero, 7
+; RV64I-NEXT: addi a7, sp, 48
; RV64I-NEXT: sd t0, 48(sp)
; RV64I-NEXT: call callee_large_scalars_exhausted_regs
; RV64I-NEXT: ld ra, 88(sp)
diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll
index bb7d933bd84d..9f65576d9786 100644
--- a/llvm/test/CodeGen/RISCV/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/vararg.ll
@@ -1441,9 +1441,9 @@ define void @va5_aligned_stack_caller() nounwind {
; ILP32-ILP32F-FPELIM-NEXT: addi a5, a0, 1311
; ILP32-ILP32F-FPELIM-NEXT: lui a0, 688509
; ILP32-ILP32F-FPELIM-NEXT: addi a6, a0, -2048
-; ILP32-ILP32F-FPELIM-NEXT: addi a2, sp, 32
; ILP32-ILP32F-FPELIM-NEXT: addi a0, zero, 1
; ILP32-ILP32F-FPELIM-NEXT: addi a1, zero, 11
+; ILP32-ILP32F-FPELIM-NEXT: addi a2, sp, 32
; ILP32-ILP32F-FPELIM-NEXT: addi a3, zero, 12
; ILP32-ILP32F-FPELIM-NEXT: addi a4, zero, 13
; ILP32-ILP32F-FPELIM-NEXT: addi a7, zero, 4
@@ -1486,9 +1486,9 @@ define void @va5_aligned_stack_caller() nounwind {
; ILP32-ILP32F-WITHFP-NEXT: addi a5, a0, 1311
; ILP32-ILP32F-WITHFP-NEXT: lui a0, 688509
; ILP32-ILP32F-WITHFP-NEXT: addi a6, a0, -2048
-; ILP32-ILP32F-WITHFP-NEXT: addi a2, s0, -32
; ILP32-ILP32F-WITHFP-NEXT: addi a0, zero, 1
; ILP32-ILP32F-WITHFP-NEXT: addi a1, zero, 11
+; ILP32-ILP32F-WITHFP-NEXT: addi a2, s0, -32
; ILP32-ILP32F-WITHFP-NEXT: addi a3, zero, 12
; ILP32-ILP32F-WITHFP-NEXT: addi a4, zero, 13
; ILP32-ILP32F-WITHFP-NEXT: addi a7, zero, 4
@@ -1530,9 +1530,9 @@ define void @va5_aligned_stack_caller() nounwind {
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a5, a0, 1311
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a0, 688509
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a6, a0, -2048
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a2, sp, 32
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, zero, 1
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, zero, 11
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a2, sp, 32
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a3, zero, 12
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a4, zero, 13
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a7, zero, 4
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