[PATCH] D40061: [ARM] Make MachineVerifier more strict about terminators

[Sam Parker via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa3e41d458130: [ARM] Make MachineVerifier more strict about terminators (authored by samparker).

Changed prior to commit:
  https://reviews.llvm.org/D40061?vs=287688&id=288200#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D40061/new/

https://reviews.llvm.org/D40061

Files:
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
  llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
  llvm/test/CodeGen/ARM/atomic-cmpxchg.ll
  llvm/test/CodeGen/ARM/call-tc.ll
  llvm/test/CodeGen/ARM/cmp-bool.ll
  llvm/test/CodeGen/ARM/cmpxchg-weak.ll
  llvm/test/CodeGen/ARM/code-placement.ll
  llvm/test/CodeGen/ARM/codesize-ifcvt.mir
  llvm/test/CodeGen/ARM/constant-islands-split-IT.mir
  llvm/test/CodeGen/ARM/csr-split.ll
  llvm/test/CodeGen/ARM/machine-sink-multidef.ll
  llvm/test/CodeGen/ARM/peephole-bitcast.ll
  llvm/test/CodeGen/ARM/reg_sequence.ll
  llvm/test/CodeGen/ARM/sched-it-debug-nodes.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/basic-tail-pred.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/exitcount.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/extending-loads.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-vcmp.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-cond-iter-count.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-add-sat.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-fabs.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-sub-sat.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-pattern-fail.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredicated-max.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-retaining.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir
  llvm/test/CodeGen/Thumb2/constant-hoisting.ll
  llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
  llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
  llvm/test/CodeGen/Thumb2/mve-fma-loops.ll
  llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
  llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
  llvm/test/CodeGen/Thumb2/mve-gather-tailpred.ll
  llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll
  llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
  llvm/test/CodeGen/Thumb2/mve-selectcc.ll
  llvm/test/DebugInfo/MIR/ARM/subregister-full-piece.mir

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