[PATCH] D86664: [GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less.

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added reviewers: paquette, arsenm, foad.
aemerson added a project: LLVM.
Herald added subscribers: kerbowa, hiraditya, rovka, nhaehnle, jvesely.
aemerson requested review of this revision.
Herald added a subscriber: wdng.

This combine previously tried to take sequences like:

  %cond = G_ICMP pred, a, b
  G_BRCOND %cond, %truebb
  G_BR %falsebb
  %truebb:
  ...
  %falsebb:
  ...

and by inverting the compare predicate and swapping branch targets, delete the G_BR and instead have a single conditional branch to the falsebb. Since in an earlier patch we have a combine to fold not(icmp) into just an inverted icmp, we don't need this combine to do as much. This patch instead generalizes the combine by just looking for:

  G_BRCOND %cond, %truebb
  G_BR %falsebb
  %truebb:
  ...
  %falsebb:
  ...

and then inverting the condition using a not (xor). The xor can be folded away in a separate combine. This change also lets us avoid some optimization code in the IRTranslator.

I also think that deleting G_BRs in the combiner is unnecessary. That's something that targets can decide to do at selection time and could simplify generic code in future.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D86664

Files:
  llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
  llvm/include/llvm/CodeGen/GlobalISel/Utils.h
  llvm/include/llvm/Target/GlobalISel/Combine.td
  llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
  llvm/lib/CodeGen/GlobalISel/Utils.cpp
  llvm/lib/Target/AArch64/AArch64Combine.td
  llvm/lib/Target/AMDGPU/AMDGPUCombine.td
  llvm/test/CodeGen/AArch64/GlobalISel/const-0.ll
  llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll

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