[llvm] 92d3e70 - [X86] Change pentium4 tuning settings and scheduler model back to their values before D83913.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 26 15:46:47 PDT 2020
Author: Craig Topper
Date: 2020-08-26T15:38:12-07:00
New Revision: 92d3e70df3ccb9e6528f0c95bae48c0a8f9b703b
URL: https://github.com/llvm/llvm-project/commit/92d3e70df3ccb9e6528f0c95bae48c0a8f9b703b
DIFF: https://github.com/llvm/llvm-project/commit/92d3e70df3ccb9e6528f0c95bae48c0a8f9b703b.diff
LOG: [X86] Change pentium4 tuning settings and scheduler model back to their values before D83913.
Clang now defaults to -march=pentium4 -mtune=generic so we don't
need modern tune settings on pentium4.
Added:
Modified:
llvm/lib/Target/X86/X86.td
llvm/test/CodeGen/X86/cfguard-x86-vectorcall.ll
llvm/test/CodeGen/X86/cmov-fp.ll
llvm/test/CodeGen/X86/post-ra-sched.ll
llvm/test/CodeGen/X86/pr34088.ll
llvm/test/CodeGen/X86/pr40539.ll
llvm/test/CodeGen/X86/slow-unaligned-mem.ll
llvm/test/DebugInfo/COFF/fpo-shrink-wrap.ll
llvm/test/DebugInfo/COFF/fpo-stack-protect.ll
llvm/test/DebugInfo/COFF/types-array.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 99eb8399d24f..f2651d658d71 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1107,20 +1107,10 @@ def : ProcModel<"pentium-m", GenericPostRAModel,
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
foreach P = ["pentium4", "pentium4m"] in {
-// def : ProcModel<P, GenericPostRAModel,
-// [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2,
-// FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
-// [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
-
- // Since 'pentium4' is the default 32-bit CPU on Linux and Windows,
- // give it more modern tunings.
- // FIXME: This wouldn't be needed if we supported mtune.
- def : ProcModel<P, SandyBridgeModel,
+ def : ProcModel<P, GenericPostRAModel,
[FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2,
FeatureFXSR, FeatureNOPL, FeatureCMOV],
- [FeatureSlow3OpsLEA, FeatureSlowDivide64,
- FeatureSlowIncDec, FeatureMacroFusion,
- FeatureInsertVZEROUPPER]>;
+ [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
}
// Intel Quark.
diff --git a/llvm/test/CodeGen/X86/cfguard-x86-vectorcall.ll b/llvm/test/CodeGen/X86/cfguard-x86-vectorcall.ll
index 4446f360ec04..25e3691913c8 100644
--- a/llvm/test/CodeGen/X86/cfguard-x86-vectorcall.ll
+++ b/llvm/test/CodeGen/X86/cfguard-x86-vectorcall.ll
@@ -1,35 +1,9 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_rip
; RUN: llc < %s -mtriple=i686-pc-windows-msvc | FileCheck %s -check-prefix=X32
; Control Flow Guard is currently only available on Windows
; Test that Control Flow Guard checks are correctly added for x86 vector calls.
define void @func_cf_vector_x86(void (%struct.HVA)* %0, %struct.HVA* %1) #0 {
-; X32-LABEL: func_cf_vector_x86:
-; X32: # %bb.0: # %entry
-; X32-NEXT: pushl %ebp
-; X32-NEXT: movl %esp, %ebp
-; X32-NEXT: andl $-16, %esp
-; X32-NEXT: subl $48, %esp
-; X32-NEXT: movl 8(%ebp), %ecx
-; X32-NEXT: movl 12(%ebp), %eax
-; X32-NEXT: movups (%eax), %xmm0
-; X32-NEXT: movups 16(%eax), %xmm1
-; X32-NEXT: movaps %xmm0, (%esp)
-; X32-NEXT: movaps %xmm1, 16(%esp)
-; X32-NEXT: movsd (%esp), %xmm4
-; X32-NEXT: movsd 8(%esp), %xmm5
-; X32-NEXT: movsd 16(%esp), %xmm6
-; X32-NEXT: movsd 24(%esp), %xmm7
-; X32-NEXT: calll *___guard_check_icall_fptr
-; X32-NEXT: movaps %xmm4, %xmm0
-; X32-NEXT: movaps %xmm5, %xmm1
-; X32-NEXT: movaps %xmm6, %xmm2
-; X32-NEXT: movaps %xmm7, %xmm3
-; X32-NEXT: calll *%ecx
-; X32-NEXT: movl %ebp, %esp
-; X32-NEXT: popl %ebp
-; X32-NEXT: retl
entry:
%2 = alloca %struct.HVA, align 8
%3 = bitcast %struct.HVA* %2 to i8*
@@ -39,6 +13,23 @@ entry:
call x86_vectorcallcc void %0(%struct.HVA inreg %5)
ret void
+ ; X32-LABEL: func_cf_vector_x86
+ ; X32: movl 12(%ebp), %eax
+ ; X32: movl 8(%ebp), %ecx
+ ; X32: movsd 24(%eax), %xmm4 # xmm4 = mem[0],zero
+ ; X32: movsd %xmm4, 24(%esp)
+ ; X32: movsd 16(%eax), %xmm5 # xmm5 = mem[0],zero
+ ; X32: movsd %xmm5, 16(%esp)
+ ; X32: movsd (%eax), %xmm6 # xmm6 = mem[0],zero
+ ; X32: movsd 8(%eax), %xmm7 # xmm7 = mem[0],zero
+ ; X32: movsd %xmm7, 8(%esp)
+ ; X32: movsd %xmm6, (%esp)
+ ; X32: calll *___guard_check_icall_fptr
+ ; X32: movaps %xmm6, %xmm0
+ ; X32: movaps %xmm7, %xmm1
+ ; X32: movaps %xmm5, %xmm2
+ ; X32: movaps %xmm4, %xmm3
+ ; X32: calll *%ecx
}
attributes #0 = { "target-cpu"="pentium4" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" }
diff --git a/llvm/test/CodeGen/X86/cmov-fp.ll b/llvm/test/CodeGen/X86/cmov-fp.ll
index 6bbad427a9b6..756324bbdfdc 100644
--- a/llvm/test/CodeGen/X86/cmov-fp.ll
+++ b/llvm/test/CodeGen/X86/cmov-fp.ll
@@ -1056,11 +1056,11 @@ define float @test16(i32 %a, i32 %b, float %x) nounwind {
define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test17:
; SSE: # %bb.0:
-; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
-; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: fxch %st(1)
+; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fcmovnbe %st(1), %st
; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl
@@ -1109,11 +1109,11 @@ define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind {
define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test18:
; SSE: # %bb.0:
-; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
-; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: fxch %st(1)
+; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fcmovnb %st(1), %st
; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl
@@ -1162,11 +1162,11 @@ define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind {
define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test19:
; SSE: # %bb.0:
-; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
-; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: fxch %st(1)
+; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fcmovb %st(1), %st
; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl
@@ -1215,11 +1215,11 @@ define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind {
define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test20:
; SSE: # %bb.0:
-; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
-; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: fxch %st(1)
+; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fcmovbe %st(1), %st
; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl
@@ -1268,13 +1268,13 @@ define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind {
define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test21:
; SSE: # %bb.0:
-; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT: fldt {{[0-9]+}}(%esp)
+; SSE-NEXT: flds {{\.LCPI.*}}
+; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: setg %al
; SSE-NEXT: testb %al, %al
-; SSE-NEXT: flds {{\.LCPI.*}}
-; SSE-NEXT: fxch %st(1)
; SSE-NEXT: fcmovne %st(1), %st
; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl
@@ -1328,13 +1328,13 @@ define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test22:
; SSE: # %bb.0:
-; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT: fldt {{[0-9]+}}(%esp)
+; SSE-NEXT: flds {{\.LCPI.*}}
+; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: setge %al
; SSE-NEXT: testb %al, %al
-; SSE-NEXT: flds {{\.LCPI.*}}
-; SSE-NEXT: fxch %st(1)
; SSE-NEXT: fcmovne %st(1), %st
; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl
@@ -1387,13 +1387,13 @@ define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind {
define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test23:
; SSE: # %bb.0:
-; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT: fldt {{[0-9]+}}(%esp)
+; SSE-NEXT: flds {{\.LCPI.*}}
+; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: setl %al
; SSE-NEXT: testb %al, %al
-; SSE-NEXT: flds {{\.LCPI.*}}
-; SSE-NEXT: fxch %st(1)
; SSE-NEXT: fcmovne %st(1), %st
; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl
@@ -1446,13 +1446,13 @@ define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind {
define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test24:
; SSE: # %bb.0:
-; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT: fldt {{[0-9]+}}(%esp)
+; SSE-NEXT: flds {{\.LCPI.*}}
+; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: setle %al
; SSE-NEXT: testb %al, %al
-; SSE-NEXT: flds {{\.LCPI.*}}
-; SSE-NEXT: fxch %st(1)
; SSE-NEXT: fcmovne %st(1), %st
; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/post-ra-sched.ll b/llvm/test/CodeGen/X86/post-ra-sched.ll
index 70882fba5060..f6de77a69883 100644
--- a/llvm/test/CodeGen/X86/post-ra-sched.ll
+++ b/llvm/test/CodeGen/X86/post-ra-sched.ll
@@ -1,6 +1,5 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i386 -mcpu=pentium4 | FileCheck %s --check-prefix=PENTIUM4
-; RUN: llc < %s -mtriple=i386 -mcpu=pentium4m | FileCheck %s --check-prefix=PENTIUM4
+; RUN: llc < %s -mtriple=i386 -mcpu=pentium4 | FileCheck %s
+; RUN: llc < %s -mtriple=i386 -mcpu=pentium4m | FileCheck %s
; RUN: llc < %s -mtriple=i386 -mcpu=pentium-m | FileCheck %s
; RUN: llc < %s -mtriple=i386 -mcpu=prescott | FileCheck %s
; RUN: llc < %s -mtriple=i386 -mcpu=nocona | FileCheck %s
@@ -10,26 +9,12 @@
; happens during the post-RA-scheduler, which should be enabled by
; default with the above specified cpus.
-; Pentium4 is the default 32-bit CPU on Linux and currently has the postRA
-; scheduler disabled. Leaving the command lines in place in case we change that.
-
@ptrs = external global [0 x i32*], align 4
@idxa = common global i32 0, align 4
@idxb = common global i32 0, align 4
@res = common global i32 0, align 4
define void @addindirect() {
-; PENTIUM4-LABEL: addindirect:
-; PENTIUM4: # %bb.0: # %entry
-; PENTIUM4-NEXT: movl idxa, %eax
-; PENTIUM4-NEXT: movl ptrs(,%eax,4), %eax
-; PENTIUM4-NEXT: movl idxb, %ecx
-; PENTIUM4-NEXT: movl ptrs(,%ecx,4), %ecx
-; PENTIUM4-NEXT: movl (%ecx), %ecx
-; PENTIUM4-NEXT: addl (%eax), %ecx
-; PENTIUM4-NEXT: movl %ecx, res
-; PENTIUM4-NEXT: retl
-;
; CHECK-LABEL: addindirect:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl idxb, %ecx
diff --git a/llvm/test/CodeGen/X86/pr34088.ll b/llvm/test/CodeGen/X86/pr34088.ll
index a57ff09cc037..6950e50dd755 100644
--- a/llvm/test/CodeGen/X86/pr34088.ll
+++ b/llvm/test/CodeGen/X86/pr34088.ll
@@ -6,7 +6,7 @@
%struct.Buffer = type { i8*, i32 }
; This test checks that the load of store %2 is not dropped.
-;
+;
define i32 @pr34088() local_unnamed_addr {
; CHECK-LABEL: pr34088:
; CHECK: # %bb.0: # %entry
@@ -18,13 +18,13 @@ define i32 @pr34088() local_unnamed_addr {
; CHECK-NEXT: andl $-16, %esp
; CHECK-NEXT: subl $32, %esp
; CHECK-NEXT: xorps %xmm0, %xmm0
+; CHECK-NEXT: movaps {{.*#+}} xmm1 = [205,205,205,205,205,205,205,205,205,205,205,205,205,205,205,205]
+; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: movaps %xmm0, (%esp)
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT: movaps {{.*#+}} xmm1 = [205,205,205,205,205,205,205,205,205,205,205,205,205,205,205,205]
-; CHECK-NEXT: movaps %xmm1, (%esp)
; CHECK-NEXT: movl $-842150451, {{[0-9]+}}(%esp) # imm = 0xCDCDCDCD
+; CHECK-NEXT: movaps %xmm1, (%esp)
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
-; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: .cfi_def_cfa %esp, 4
diff --git a/llvm/test/CodeGen/X86/pr40539.ll b/llvm/test/CodeGen/X86/pr40539.ll
index f52fec51203a..f2135cd2e73b 100644
--- a/llvm/test/CodeGen/X86/pr40539.ll
+++ b/llvm/test/CodeGen/X86/pr40539.ll
@@ -40,6 +40,7 @@ define zeroext i1 @_Z8test_cosv() {
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: divss {{\.LCPI.*}}, %xmm0
; CHECK-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; CHECK-NEXT: flds {{[0-9]+}}(%esp)
@@ -48,7 +49,6 @@ define zeroext i1 @_Z8test_cosv() {
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: fstps (%esp)
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: ucomiss %xmm0, %xmm1
; CHECK-NEXT: setae %cl
; CHECK-NEXT: ucomiss {{\.LCPI.*}}, %xmm0
diff --git a/llvm/test/CodeGen/X86/slow-unaligned-mem.ll b/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
index 295fdfb5a261..f2c7c2fa4a56 100644
--- a/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
+++ b/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
@@ -3,6 +3,8 @@
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefix=SLOW
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefix=SLOW
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefix=SLOW
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=SLOW
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=SLOW
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=SLOW
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=SLOW
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=SLOW
@@ -12,10 +14,6 @@
; Intel chips with fast unaligned memory accesses
-; Marked fast because this is the default 32-bit mode CPU in clang.
-; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=FAST
-; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=FAST
-
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=silvermont 2>&1 | FileCheck %s --check-prefix=FAST
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=nehalem 2>&1 | FileCheck %s --check-prefix=FAST
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=westmere 2>&1 | FileCheck %s --check-prefix=FAST
diff --git a/llvm/test/DebugInfo/COFF/fpo-shrink-wrap.ll b/llvm/test/DebugInfo/COFF/fpo-shrink-wrap.ll
index 719d69d16a62..08aecdac5b79 100644
--- a/llvm/test/DebugInfo/COFF/fpo-shrink-wrap.ll
+++ b/llvm/test/DebugInfo/COFF/fpo-shrink-wrap.ll
@@ -40,7 +40,7 @@
; OBJ: SubSectionType: FrameData (0xF5)
; OBJ: FrameData {
; OBJ: RvaStart: 0x0
-; OBJ: CodeSize: 0x36
+; OBJ: CodeSize: 0x34
; OBJ: PrologSize: 0x9
; OBJ: FrameFunc [
; OBJ-NEXT: $T0 .raSearch =
@@ -50,7 +50,7 @@
; OBJ: }
; OBJ: FrameData {
; OBJ: RvaStart: 0x7
-; OBJ: CodeSize: 0x2F
+; OBJ: CodeSize: 0x2D
; OBJ: PrologSize: 0x2
; OBJ: FrameFunc [
; OBJ-NEXT: $T0 .raSearch =
@@ -61,7 +61,7 @@
; OBJ: }
; OBJ: FrameData {
; OBJ: RvaStart: 0x8
-; OBJ: CodeSize: 0x2E
+; OBJ: CodeSize: 0x2C
; OBJ: PrologSize: 0x1
; OBJ: FrameFunc [
; OBJ-NEXT: $T0 .raSearch =
@@ -73,7 +73,7 @@
; OBJ: }
; OBJ: FrameData {
; OBJ: RvaStart: 0x9
-; OBJ: CodeSize: 0x2D
+; OBJ: CodeSize: 0x2B
; OBJ: PrologSize: 0x0
; OBJ: FrameFunc [
; OBJ-NEXT: $T0 .raSearch =
diff --git a/llvm/test/DebugInfo/COFF/fpo-stack-protect.ll b/llvm/test/DebugInfo/COFF/fpo-stack-protect.ll
index c604234a6055..26fe7c49e7ac 100644
--- a/llvm/test/DebugInfo/COFF/fpo-stack-protect.ll
+++ b/llvm/test/DebugInfo/COFF/fpo-stack-protect.ll
@@ -15,9 +15,9 @@
; CHECK: subl $20, %esp
; CHECK: .cv_fpo_stackalloc 20
; CHECK: .cv_fpo_endprologue
-; CHECK: movl 28(%esp), %esi
; CHECK: ___security_cookie
+; CHECK: movl 28(%esp), %esi
; CHECK: movl %esi, {{[0-9]*}}(%esp)
; CHECK: movl %esi, {{[0-9]*}}(%esp)
; CHECK: movl %esi, {{[0-9]*}}(%esp)
@@ -30,7 +30,7 @@
; CHECK: addl $20, %esp
; CHECK: popl %esi
; CHECK: retl
-; CHECK: Ltmp2:
+; CHECK: Ltmp3:
; CHECK: .cv_fpo_endproc
; ModuleID = 't.c'
diff --git a/llvm/test/DebugInfo/COFF/types-array.ll b/llvm/test/DebugInfo/COFF/types-array.ll
index 19ddcf9ffe2c..2962f970aca1 100644
--- a/llvm/test/DebugInfo/COFF/types-array.ll
+++ b/llvm/test/DebugInfo/COFF/types-array.ll
@@ -51,7 +51,7 @@
; CHECK: PtrParent: 0x0
; CHECK: PtrEnd: 0x0
; CHECK: PtrNext: 0x0
-; CHECK: CodeSize: 0x2A
+; CHECK: CodeSize: 0x39
; CHECK: DbgStart: 0x0
; CHECK: DbgEnd: 0x0
; CHECK: FunctionType: f (0x1002)
@@ -73,7 +73,7 @@
; CHECK: LocalVariableAddrRange {
; CHECK: OffsetStart: .text+0x6
; CHECK: ISectStart: 0x0
-; CHECK: Range: 0x24
+; CHECK: Range: 0x33
; CHECK: }
; CHECK: }
; CHECK: ProcEnd {
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