[PATCH] D86613: [ARM][LowOverheadLoops] Liveouts and reductions

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added a comment.

That's good amount of red/deletions!
Read this for the first time, and looks very reasonable. I have one question inline for now while I go over this again.



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Comment at: llvm/include/llvm/CodeGen/ReachingDefAnalysis.h:208
+  void getGlobalReachingDefs(MachineInstr *MI, int PhysReg,
+                             InstSet &Uses) const;
+
----------------
nit: `Uses` -> `Defs`?


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Comment at: llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp:643
+    return !isVectorPredicated(Def) &&
+           Def->getOpcode() == ARM::MVE_VMOVimmi32 &&
+           Def->getOperand(1).getImm() == 0;
----------------
Is this the only instruction that could zero initialise that def?


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Comment at: llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp:656
+    // - If it only consumes false lanes zero or constant 0 (vmov #0)
+    // - If it's predicated, it only matters that it's def register already has
+    //   false lane zeros, so we can ignore its uses.
----------------
nit: it's -> its


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  https://reviews.llvm.org/D86613/new/

https://reviews.llvm.org/D86613