[PATCH] D86468: [WIP][GlobalISel] CSE copies

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

In D86468#2234049 <https://reviews.llvm.org/D86468#2234049>, @arsenm wrote:

> I always thought all the stuff SelectionDAG::getNode tried to do was insane, and a large part of why the DAG is so slow.

If you're ever going to do these simplifications, then surely it makes sense to do them up front so you don't have to create the MIR, rather than doing them in a later combine/simplification pass?

> How often do these trivially simplifiable situations actually get produced during legalization and combines? I would expect it's pretty rare

I tried a quick hack to simplify integer arithmetic in MIRBuilder, and you can see the effect on AMDGPU legalization tests here: https://github.com/jayfoad/llvm-project/commit/00d98a70c4dc8e8db2f8465104a5e65ca12409f5



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Comment at: llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp:168-172
+    if (Dst.getDstOpKind() == DstOp::DstType::Ty_LLT &&
+        Dst.getLLTTy(*getMRI()) == Src.getLLTTy(*getMRI())) {
+      Register SrcReg = Src.getReg();
+      assert(SrcReg.isVirtual());
+      return MachineInstrBuilder(getMF(), getMRI()->getVRegDef(SrcReg));
----------------
arsenm wrote:
> This would also have to be careful to not fold away cross class or bank copies
I ran into this problem with AArch64InstructionSelector::fixupPHIOpBanks but I'm not sure hwo to handle it, since the register bank is not set until after the copy has been created.


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