[PATCH] D86601: [LegalizeTypes] Add ROTL/ROTR to ScalarizeVectorResult.

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.
foad requested review of this revision.

We can scalarize these just like any other binary operation.

Fixes failures seen after D77152 <https://reviews.llvm.org/D77152>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D86601

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -146,6 +146,8 @@
   case ISD::SHL:
   case ISD::SRA:
   case ISD::SRL:
+  case ISD::ROTL:
+  case ISD::ROTR:
     R = ScalarizeVecRes_BinOp(N);
     break;
   case ISD::FMA:


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