[PATCH] D86548: [SVE][CodeGen] Legalisation of truncate for scalable vectors

Eli Friedman via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 25 14:57:02 PDT 2020


efriedma added a comment.

It's probably worth considering adding a target-independent opcode for this sort of truncate, but I guess this approach is okay, at least for now.



================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:4681
 
 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
   SDLoc dl(N);
----------------
How do we end up here? I guess we split the truncate into two truncs, and then concatenate the two truncates?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:956
+      } else
+        setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
     }
----------------
I'd prefer to list out the relevant types more explicitly; the set of illegal types listed in integer_scalable_vector_valuetypes() could change if other targets need additional scalable types.  Can we use the same `{MVT::nxv8i8, MVT::nxv4i16, MVT::nxv2i32}` list we use for EXTRACT_SUBVECTOR?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8949
+    if (!Op0VT.isInteger() || !Op1VT.isInteger())
+      return SDValue();
+
----------------
Do we need to check the result type is legal?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8971
+      SDValue LoVec0;
+      if (Vec0.getOpcode() == AArch64ISD::UZP1 && Vec0->getOperand(1).isUndef())
+        LoVec0 = Vec0->getOperand(0);
----------------
Is the `Vec0->getOperand(1).isUndef()` check actually necessary?

Can we have the same set of checks for optimizing the "other" half in the low and high cases?  Some of them won't be immediately useful, but it helps make the logic more clear.


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