[llvm] 514d6e9 - [SDAG] Improve MemSDNode::getBasePtr

[Krzysztof Parzyszek via llvm-commits]

Author: Krzysztof Parzyszek
Date: 2020-08-25T15:19:52-05:00
New Revision: 514d6e9a8d91e739292c9024d677b8d3c6d43f0c

URL: https://github.com/llvm/llvm-project/commit/514d6e9a8d91e739292c9024d677b8d3c6d43f0c
DIFF: https://github.com/llvm/llvm-project/commit/514d6e9a8d91e739292c9024d677b8d3c6d43f0c.diff

LOG: [SDAG] Improve MemSDNode::getBasePtr

It returned getOperand(1), except for STORE for which it returned
getOperand(2). Handle MSTORE, MGATHER, and MSCATTER as well.

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Removed: 
    


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diff  --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index 7c2b49087edd..cde075f41f73 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -1379,8 +1379,18 @@ class MemSDNode : public SDNode {
   }
 
   const SDValue &getChain() const { return getOperand(0); }
+
   const SDValue &getBasePtr() const {
-    return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
+    switch (getOpcode()) {
+    case ISD::STORE:
+    case ISD::MSTORE:
+      return getOperand(2);
+    case ISD::MGATHER:
+    case ISD::MSCATTER:
+      return getOperand(3);
+    default:
+      return getOperand(1);
+    }
   }
 
   // Methods to support isa and dyn_cast
@@ -2292,9 +2302,6 @@ class MaskedLoadStoreSDNode : public MemSDNode {
   // MaskedLoadSDNode (Chain, ptr, offset, mask, passthru)
   // MaskedStoreSDNode (Chain, data, ptr, offset, mask)
   // Mask is a vector of i1 elements
-  const SDValue &getBasePtr() const {
-    return getOperand(getOpcode() == ISD::MLOAD ? 1 : 2);
-  }
   const SDValue &getOffset() const {
     return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
   }