[llvm] dcef5e0 - [Hexagon] Remove (redundant) HexagonISelLowering::isHvxOperation(SDValue)

[Krzysztof Parzyszek via llvm-commits]

Author: Krzysztof Parzyszek
Date: 2020-08-25T11:45:08-05:00
New Revision: dcef5e0c376c9ef558186ca8939b857bf7f76d56

URL: https://github.com/llvm/llvm-project/commit/dcef5e0c376c9ef558186ca8939b857bf7f76d56
DIFF: https://github.com/llvm/llvm-project/commit/dcef5e0c376c9ef558186ca8939b857bf7f76d56.diff

LOG: [Hexagon] Remove (redundant) HexagonISelLowering::isHvxOperation(SDValue)

Use isHvxOperation(SDNode*) instead.

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
    llvm/lib/Target/Hexagon/HexagonISelLowering.h
    llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index b938aa1168ca..90873fcb34d6 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -3025,7 +3025,7 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR)
     return LowerINLINEASM(Op, DAG);
 
-  if (isHvxOperation(Op)) {
+  if (isHvxOperation(Op.getNode())) {
     // If HVX lowering returns nothing, try the default lowering.
     if (SDValue V = LowerHvxOperation(Op, DAG))
       return V;
@@ -3132,13 +3132,13 @@ HexagonTargetLowering::ReplaceNodeResults(SDNode *N,
 SDValue
 HexagonTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
       const {
-  SDValue Op(N, 0);
-  if (isHvxOperation(Op)) {
+  if (isHvxOperation(N)) {
     if (SDValue V = PerformHvxDAGCombine(N, DCI))
       return V;
     return SDValue();
   }
 
+  SDValue Op(N, 0);
   const SDLoc &dl(Op);
   unsigned Opc = Op.getOpcode();
 

diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index 7d6e6b6185c8..7aee7df917b4 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -479,7 +479,6 @@ namespace HexagonISD {
     findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
         const override;
 
-    bool isHvxOperation(SDValue Op) const;
     bool isHvxOperation(SDNode *N) const;
     SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const;
     void LowerHvxOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,

diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 5da82244e69c..5b6fd00e2765 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -1802,17 +1802,6 @@ HexagonTargetLowering::PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
   return SDValue();
 }
 
-bool
-HexagonTargetLowering::isHvxOperation(SDValue Op) const {
-  // If the type of the result, or any operand type are HVX vector types,
-  // this is an HVX operation.
-  return Subtarget.isHVXVectorType(ty(Op), true) ||
-         llvm::any_of(Op.getNode()->ops(),
-                      [this] (SDValue V) {
-                        return Subtarget.isHVXVectorType(ty(V), true);
-                      });
-}
-
 bool
 HexagonTargetLowering::isHvxOperation(SDNode *N) const {
   // If the type of any result, or any operand type are HVX vector types,