[PATCH] D86518: [RISC-V] fmv.s/fmv.d should be as cheap as a move
Alexander Richardson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 25 03:48:47 PDT 2020
arichardson created this revision.
arichardson added reviewers: asb, jrtc27, luismarques.
Herald added subscribers: llvm-commits, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.
arichardson requested review of this revision.
Herald added a subscriber: MaskRay.
Since the canonical floatig-point move is fsgnj rd, rs, rs, we should
handle this case in RISCVInstrInfo::isAsCheapAsAMove().
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D86518
Files:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -515,6 +515,11 @@
switch (Opcode) {
default:
break;
+ case RISCV::FSGNJ_D:
+ case RISCV::FSGNJ_S:
+ // The canonical floatig-point move is fsgnj rd, rs, rs.
+ return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
+ MI.getOperand(1).getReg() == MI.getOperand(2).getReg();
case RISCV::ADDI:
case RISCV::ORI:
case RISCV::XORI:
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D86518.287616.patch
Type: text/x-patch
Size: 580 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200825/89f54c56/attachment.bin>
More information about the llvm-commits
mailing list