[PATCH] D84659: [PowerPC] Handle SUBFIC in reg+reg -> reg+imm transformation
Nemanja Ivanovic via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 24 14:23:22 PDT 2020
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc485343c8310: [PowerPC] Handle SUBFIC in reg+reg -> reg+imm transformation (authored by nemanjai).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D84659/new/
https://reviews.llvm.org/D84659
Files:
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/test/CodeGen/PowerPC/pr44183.ll
Index: llvm/test/CodeGen/PowerPC/pr44183.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/pr44183.ll
+++ llvm/test/CodeGen/PowerPC/pr44183.ll
@@ -8,37 +8,33 @@
; CHECK-LABEL: _ZN1m1nEv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0
-; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
-; CHECK-NEXT: stdu r1, -64(r1)
+; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: mr r30, r3
-; CHECK-NEXT: li r3, 4
; CHECK-NEXT: ld r4, 16(r30)
; CHECK-NEXT: ld r5, 8(r30)
-; CHECK-NEXT: subfic r29, r3, 64
-; CHECK-NEXT: rldicl r3, r5, 60, 4
-; CHECK-NEXT: sld r4, r4, r29
-; CHECK-NEXT: lwz r5, 36(r30)
-; CHECK-NEXT: or r3, r4, r3
-; CHECK-NEXT: rlwinm r3, r3, 31, 0, 0
-; CHECK-NEXT: clrlwi r4, r5, 31
+; CHECK-NEXT: lwz r6, 36(r30)
+; CHECK-NEXT: rldicl r5, r5, 60, 4
+; CHECK-NEXT: sldi r4, r4, 60
+; CHECK-NEXT: or r4, r4, r5
+; CHECK-NEXT: rlwinm r3, r4, 31, 0, 0
+; CHECK-NEXT: clrlwi r4, r6, 31
; CHECK-NEXT: or r4, r4, r3
; CHECK-NEXT: bl _ZN1llsE1d
; CHECK-NEXT: nop
; CHECK-NEXT: ld r3, 16(r30)
; CHECK-NEXT: ld r4, 8(r30)
; CHECK-NEXT: rldicl r4, r4, 60, 4
-; CHECK-NEXT: sld r3, r3, r29
+; CHECK-NEXT: sldi r3, r3, 60
; CHECK-NEXT: or r3, r3, r4
; CHECK-NEXT: sldi r3, r3, 31
; CHECK-NEXT: clrldi r4, r3, 32
; CHECK-NEXT: bl _ZN1llsE1d
; CHECK-NEXT: nop
-; CHECK-NEXT: addi r1, r1, 64
+; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
entry:
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -3760,6 +3760,20 @@
}
return false;
}
+ case PPC::SUBFIC:
+ case PPC::SUBFIC8: {
+ // Only transform this if the CARRY implicit operand is dead.
+ if (MI.getNumOperands() > 3 && !MI.getOperand(3).isDead())
+ return false;
+ int64_t Minuend = MI.getOperand(2).getImm();
+ if (isInt<16>(Minuend - SExtImm)) {
+ ReplaceWithLI = true;
+ Is64BitLI = Opc == PPC::SUBFIC8;
+ NewImm = Minuend - SExtImm;
+ break;
+ }
+ return false;
+ }
case PPC::RLDICL:
case PPC::RLDICL_rec:
case PPC::RLDICL_32:
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