[PATCH] D85364: [SVE][WIP] Implement lowering for fixed width select

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally updated this revision to Diff 287473.
cameron.mcinally added a comment.

Updating to exhibit the problem mentioned in D85546 <https://reviews.llvm.org/D85546>. One way to see the issue is:

  llc -aarch64-sve-vector-bits-min=256 -asm-verbose=0 < llvm-project/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll

The problem originates in Legalize. `DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(...)` will produce fixed length DAGs like this:

      t18: v8i16 = any_extend t16
    t20: v8i16 = sign_extend_inreg t18, ValueType:ch:v8i1
  t12: v8f16 = vselect t20, t10, t11

This ISD::SIGN_EXTEND operation expects both the result and operand type to be the same.

However, when we go to lower this to AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU, that operation expects a half vector type for the operand. Here's a special case -- for illustrative purposes only:

  def : Pat<(sext_inreg (nxv8i16 ZPR:$Zs), nxv8i8),  (SXTB_ZPmZ_H (IMPLICIT_DEF), (PTRUE_H 31), ZPR:$Zs)>;

At the surface, it's not really a big problem, since nxv8i8 and nxv8i16 are really the same register class. I just can't find a good way to **bitcast** between the two types with the fixed length lowering utilites.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85364/new/

https://reviews.llvm.org/D85364

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll

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