[PATCH] D86480: [RISC-V] ADDI/ORI x, 0 should be as cheap as a move

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

I think ORI and XORI should go together, as they're both moves when the immediate is 0. ADDI with 0 is special as the canonical move instruction, whereas ORI/XORI with 0 are not necessarily moves in microarchitectures, so I don't know whether they should be recognised here or not.

`C.MV rd, rs` is also `ADD rd, x0, rs` rather than `ADDI rd, rs, 0` so it might make sense to match ADD with rs1 == x0.


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  https://reviews.llvm.org/D86480/new/

https://reviews.llvm.org/D86480