[PATCH] D86479: [AArch64][GlobalISel] Don't emit a branch for a fallthrough G_BR.

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added a reviewer: paquette.
aemerson added a project: LLVM.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka.
aemerson requested review of this revision.

I'm going to later change the IRTranslator to not remove unnecessary fallthrough G_BRs and leave it down to the target. Implement this in earlySelect() before the tablegen selector can select it.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D86479

Files:
  llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-xor.mir


Index: llvm/test/CodeGen/AArch64/GlobalISel/select-xor.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/select-xor.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/select-xor.mir
@@ -132,7 +132,6 @@
   ; CHECK-LABEL: name: xor_constant_n1_s32_gpr_2bb
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
   ; CHECK:   [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY]]
Index: llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir
@@ -19,7 +19,6 @@
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   liveins: $w0, $x0, $lr
   ; CHECK:   [[COPY:%[0-9]+]]:gpr64sp = COPY $lr
-  ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
   ; CHECK:   $x0 = COPY [[COPY1]]
@@ -47,7 +46,6 @@
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   liveins: $w0, $x0, $lr
   ; CHECK:   [[COPY:%[0-9]+]]:gpr64sp = COPY $lr
-  ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
   ; CHECK:   $x0 = COPY [[COPY1]]
@@ -78,7 +76,6 @@
   ; CHECK:   liveins: $w0, $x0, $lr
   ; CHECK:   [[COPY:%[0-9]+]]:gpr64sp = COPY $lr
   ; CHECK:   [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
-  ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $x0 = COPY [[COPY1]]
   ; CHECK:   [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY]]
Index: llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
@@ -35,7 +35,6 @@
   ; CHECK:   BR %6
   ; CHECK: bb.2:
   ; CHECK:   successors: %bb.3(0x80000000)
-  ; CHECK:   B %bb.3
   ; CHECK: bb.3:
   ; CHECK:   RET_ReallyLR
   bb.1:
Index: llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
@@ -330,7 +330,6 @@
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
-  ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
   ; CHECK:   $w0 = COPY [[ADDWri]]
Index: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
===================================================================
--- llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -1755,6 +1755,13 @@
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
   switch (I.getOpcode()) {
+  case TargetOpcode::G_BR:
+    // If the branch jumps to the fallthrough block, don't bother emitting it.
+    if (MBB.isLayoutSuccessor(I.getOperand(0).getMBB())) {
+      I.eraseFromParent();
+      return true;
+    }
+    break;
   case TargetOpcode::G_SHL:
     return earlySelectSHL(I, MRI);
   case TargetOpcode::G_CONSTANT: {


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