[PATCH] D86460: [InstCombine] improve demanded element analysis for vector insert-of-extract

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:1168
+    Value *Vec;
+    if (PreInsertDemandedElts == 0 &&
+        match(I->getOperand(1),
----------------
aqjune wrote:
> lebedev.ri wrote:
> > To check my understanding, `@ins_of_ext_wrong_demand` is fine
> > because for it `PreInsertDemandedElts` is not `0`, right?
> I think so - IIUC, each `insertelement` instruction zero-izes IdxNo bit of `PreInsertDemandedElts`, and in case of `@ins_of_ext_wrong_demand`, there aren't sufficient `insertelement`s to make `PreInsertDemandedElts` fully zero.
That is correct. In the negative test, element 3 is still demanded, so `PreInsertDemandedElts` is 0b1000 when we get here from the last insertelement.
Demanded elements/bits always requires some mental exercise to follow how it is working. If anyone has suggestions to improve the comments or code, let me know.


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  https://reviews.llvm.org/D86460/new/

https://reviews.llvm.org/D86460