[PATCH] D60413: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope added a comment.

I've submitted a PR, https://bugs.llvm.org/show_bug.cgi?id=47296, regarding the debuginfo problem.

For know I simply hardcoded a condition to avoid the transform downstream for out target (when vectors are involved), as a workaround to the problem with now having any simple way to lower a vector zext.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D60413