[PATCH] D82709: [MachineLICM] [PowerPC] hoisting rematerializable cheap instructions based on register pressure.

[ChenZheng via Phabricator via llvm-commits]

shchenz added a comment.

Hi @qcolombet the log for the new added case(With the change in https://reviews.llvm.org/D82709#2121904) is put https://reviews.llvm.org/P8231

We expect that `outteruse1` should not be spilled, for example, you can check virtual register `%0` in the log file. 
This can be achieved by remat all `LIS` to its use inside the loop. My first try is to do this in MachineLICM and find it works. After hoisting `LIS` based on register pressure, there is no spill both inside the inner loop and outter loop.

machine LICM  expects greedy register allocation will remat all the `LIS` and so currently machine LICM hoists these remat instructions without considering register pressure.

But inside register allocation, that is not always the case.
for now  `%0`  has high priority (big live interval size) but low spill weight (used in outer loop), and it is spilled before remat all `LIS`. So spill for `%0` is kept in outer loop after the RA. 
But as we can see, after RA, there are some remat instructions like `%267` ~ `%309` can be remat to the inner loop and reuse `%x9` like other `LIS` instructions already inside that loop.

Do you have any idea about how to fix this in greedy RA? Thanks.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82709/new/

https://reviews.llvm.org/D82709