[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.

LGTM aside from a couple of minor nits.



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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13405
+  // This combine is only eligible for a BUILD_VECTOR of v1i128.
+  // Other return types are not valid for the LXVRZX replacement.
+  if (N->getValueType(0) != MVT::v1i128)
----------------
This line is redundant. Please remove it.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13424
+  // Ensure that the load from the narrow width is being zero extended to i128.
+  if (!ValidLDType || (LD->getValueType(0) != MVT::i128) ||
+      (LD->getExtensionType() != ISD::ZEXTLOAD &&
----------------
The second condition was already checked on line 13604. You can omit  it here.


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