[llvm] f7e4e87 - [DSE, MemorySSA] Regenerate check lines for atomic.ll tests.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 21 02:18:24 PDT 2020
Author: Florian Hahn
Date: 2020-08-21T10:18:06+01:00
New Revision: f7e4e87df34fe140020180a0ea8f7bde14b3a62f
URL: https://github.com/llvm/llvm-project/commit/f7e4e87df34fe140020180a0ea8f7bde14b3a62f
DIFF: https://github.com/llvm/llvm-project/commit/f7e4e87df34fe140020180a0ea8f7bde14b3a62f.diff
LOG: [DSE,MemorySSA] Regenerate check lines for atomic.ll tests.
Added:
Modified:
llvm/test/Transforms/DeadStoreElimination/MSSA/atomic.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/atomic.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/atomic.ll
index ba4bc2ed5c4c..f2d5d28c0b2a 100644
--- a/llvm/test/Transforms/DeadStoreElimination/MSSA/atomic.ll
+++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/atomic.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -basic-aa -dse -enable-dse-memoryssa -S < %s | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
@@ -14,9 +15,11 @@ declare void @randomop(i32*)
; DSE across unordered store (allowed)
define void @test1() {
-; CHECK-LABEL: test1
-; CHECK-NOT: store i32 0
-; CHECK: store i32 1
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: store atomic i32 0, i32* @y unordered, align 4
+; CHECK-NEXT: store i32 1, i32* @x, align 4
+; CHECK-NEXT: ret void
+;
store i32 0, i32* @x
store atomic i32 0, i32* @y unordered, align 4
store i32 1, i32* @x
@@ -25,9 +28,10 @@ define void @test1() {
; DSE remove unordered store (allowed)
define void @test4() {
-; CHECK-LABEL: test4
-; CHECK-NOT: store atomic
-; CHECK: store i32 1
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: store i32 1, i32* @x, align 4
+; CHECK-NEXT: ret void
+;
store atomic i32 0, i32* @x unordered, align 4
store i32 1, i32* @x
ret void
@@ -35,8 +39,10 @@ define void @test4() {
; DSE unordered store overwriting non-atomic store (allowed)
define void @test5() {
-; CHECK-LABEL: test5
-; CHECK: store atomic i32 1
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: store atomic i32 1, i32* @x unordered, align 4
+; CHECK-NEXT: ret void
+;
store i32 0, i32* @x
store atomic i32 1, i32* @x unordered, align 4
ret void
@@ -44,9 +50,9 @@ define void @test5() {
; DSE no-op unordered atomic store (allowed)
define void @test6() {
-; CHECK-LABEL: test6
-; CHECK-NOT: store
-; CHECK: ret void
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: ret void
+;
%x = load atomic i32, i32* @x unordered, align 4
store atomic i32 %x, i32* @x unordered, align 4
ret void
@@ -55,8 +61,11 @@ define void @test6() {
; DSE seq_cst store (be conservative; DSE doesn't have infrastructure
; to reason about atomic operations).
define void @test7() {
-; CHECK-LABEL: test7
-; CHECK: store atomic
+; CHECK-LABEL: @test7(
+; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT: store atomic i32 0, i32* [[A]] seq_cst, align 4
+; CHECK-NEXT: ret void
+;
%a = alloca i32
store atomic i32 0, i32* %a seq_cst, align 4
ret void
@@ -65,9 +74,13 @@ define void @test7() {
; DSE and seq_cst load (be conservative; DSE doesn't have infrastructure
; to reason about atomic operations).
define i32 @test8() {
-; CHECK-LABEL: test8
-; CHECK: store
-; CHECK: load atomic
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT: call void @randomop(i32* [[A]])
+; CHECK-NEXT: store i32 0, i32* [[A]], align 4
+; CHECK-NEXT: [[X:%.*]] = load atomic i32, i32* @x seq_cst, align 4
+; CHECK-NEXT: ret i32 [[X]]
+;
%a = alloca i32
call void @randomop(i32* %a)
store i32 0, i32* %a, align 4
@@ -77,9 +90,12 @@ define i32 @test8() {
; DSE across monotonic load (forbidden since the eliminated store is atomic)
define i32 @test11() {
-; CHECK-LABEL: test11
-; CHECK: store atomic i32 0
-; CHECK: store atomic i32 1
+; CHECK-LABEL: @test11(
+; CHECK-NEXT: store atomic i32 0, i32* @x monotonic, align 4
+; CHECK-NEXT: [[X:%.*]] = load atomic i32, i32* @y monotonic, align 4
+; CHECK-NEXT: store atomic i32 1, i32* @x monotonic, align 4
+; CHECK-NEXT: ret i32 [[X]]
+;
store atomic i32 0, i32* @x monotonic, align 4
%x = load atomic i32, i32* @y monotonic, align 4
store atomic i32 1, i32* @x monotonic, align 4
@@ -88,9 +104,12 @@ define i32 @test11() {
; DSE across monotonic store (forbidden since the eliminated store is atomic)
define void @test12() {
-; CHECK-LABEL: test12
-; CHECK: store atomic i32 0
-; CHECK: store atomic i32 1
+; CHECK-LABEL: @test12(
+; CHECK-NEXT: store atomic i32 0, i32* @x monotonic, align 4
+; CHECK-NEXT: store atomic i32 42, i32* @y monotonic, align 4
+; CHECK-NEXT: store atomic i32 1, i32* @x monotonic, align 4
+; CHECK-NEXT: ret void
+;
store atomic i32 0, i32* @x monotonic, align 4
store atomic i32 42, i32* @y monotonic, align 4
store atomic i32 1, i32* @x monotonic, align 4
@@ -99,9 +118,13 @@ define void @test12() {
; But DSE is not allowed across a release-acquire pair.
define i32 @test15() {
-; CHECK-LABEL: test15
-; CHECK: store i32 0
-; CHECK: store i32 1
+; CHECK-LABEL: @test15(
+; CHECK-NEXT: store i32 0, i32* @x, align 4
+; CHECK-NEXT: store atomic i32 0, i32* @y release, align 4
+; CHECK-NEXT: [[X:%.*]] = load atomic i32, i32* @y acquire, align 4
+; CHECK-NEXT: store i32 1, i32* @x, align 4
+; CHECK-NEXT: ret i32 [[X]]
+;
store i32 0, i32* @x
store atomic i32 0, i32* @y release, align 4
%x = load atomic i32, i32* @y acquire, align 4
@@ -134,8 +157,8 @@ define void @test_store_atomic(i32* %Q) {
; We can NOT optimize release atomic loads or stores.
define void @test_store_atomic_release(i32* %Q) {
; CHECK-LABEL: @test_store_atomic_release(
-; CHECK-NEXT: load
-; CHECK-NEXT: store atomic
+; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[Q:%.*]], align 4
+; CHECK-NEXT: store atomic i32 [[A]], i32* [[Q]] release, align 4
; CHECK-NEXT: ret void
;
%a = load i32, i32* %Q
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