[PATCH] D86225: [AArch64] Optimize instruction selection for certain vector shuffles

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks. One last question about this new bit of code.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7976-7979
+      bool IsWidened = V1.getValueType().getSizeInBits() != VT.getSizeInBits();
+      EVT ResVT = IsWidened ? getWidenedVectorTy(VT) : VT;
+      // Cast back to the original or the widended type
+      return DAG.getBitcast(ResVT, V1);
----------------
I'm not sure I see when will this happen. Aren't we returning a node that isn't of type VT? I think that would cause problems. It looks like the output from constructDup should be of type VT, unless I'm missing something.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D86225/new/

https://reviews.llvm.org/D86225