[llvm] 8372e47 - [NFCI][SVE] Move fixed length i32/i64 SDIV tests
Cameron McInally via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 20 12:46:37 PDT 2020
Author: Cameron McInally
Date: 2020-08-20T14:46:26-05:00
New Revision: 8372e47bb968803c139d0df54ea49c7e4e2488d1
URL: https://github.com/llvm/llvm-project/commit/8372e47bb968803c139d0df54ea49c7e4e2488d1
DIFF: https://github.com/llvm/llvm-project/commit/8372e47bb968803c139d0df54ea49c7e4e2488d1.diff
LOG: [NFCI][SVE] Move fixed length i32/i64 SDIV tests
Move fixed length SDIV tests from sve-fixed-length-int-arith.ll to sve-fixed-length-int-div.ll. The former uses CHECK lines that verify legalization decisions. That's overkill for the i8/i16 SDIV tests, since they have a tricky legalization.
Added:
Modified:
llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
index e4a0ced83e26..a42f89d90e21 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
@@ -419,170 +419,6 @@ define void @add_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
; VBYTES because the add tests already validate the legalisation code paths.
;
-;
-; SDIV
-;
-
-; Vector v2i32 sdiv are not legal for NEON so use SVE when available.
-define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
-; CHECK-LABEL: sdiv_v2i32:
-; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),2)]]
-; CHECK: sdiv z0.s, [[PG]]/m, z0.s, z1.s
-; CHECK: ret
- %res = sdiv <2 x i32> %op1, %op2
- ret <2 x i32> %res
-}
-
-; Vector v4i32 sdiv are not legal for NEON so use SVE when available.
-define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
-; CHECK-LABEL: sdiv_v4i32:
-; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),4)]]
-; CHECK: sdiv z0.s, [[PG]]/m, z0.s, z1.s
-; CHECK: ret
- %res = sdiv <4 x i32> %op1, %op2
- ret <4 x i32> %res
-}
-
-define void @sdiv_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
-; CHECK-LABEL: sdiv_v8i32:
-; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
-; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
-; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
-; CHECK: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
-; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
-; CHECK: ret
- %op1 = load <8 x i32>, <8 x i32>* %a
- %op2 = load <8 x i32>, <8 x i32>* %b
- %res = sdiv <8 x i32> %op1, %op2
- store <8 x i32> %res, <8 x i32>* %a
- ret void
-}
-
-define void @sdiv_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
-; CHECK-LABEL: sdiv_v16i32:
-; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
-; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
-; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
-; CHECK: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
-; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
-; CHECK: ret
- %op1 = load <16 x i32>, <16 x i32>* %a
- %op2 = load <16 x i32>, <16 x i32>* %b
- %res = sdiv <16 x i32> %op1, %op2
- store <16 x i32> %res, <16 x i32>* %a
- ret void
-}
-
-define void @sdiv_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
-; CHECK-LABEL: sdiv_v32i32:
-; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
-; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
-; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
-; CHECK: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
-; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
-; CHECK: ret
- %op1 = load <32 x i32>, <32 x i32>* %a
- %op2 = load <32 x i32>, <32 x i32>* %b
- %res = sdiv <32 x i32> %op1, %op2
- store <32 x i32> %res, <32 x i32>* %a
- ret void
-}
-
-define void @sdiv_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
-; CHECK-LABEL: sdiv_v64i32:
-; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
-; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
-; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
-; CHECK: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
-; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
-; CHECK: ret
- %op1 = load <64 x i32>, <64 x i32>* %a
- %op2 = load <64 x i32>, <64 x i32>* %b
- %res = sdiv <64 x i32> %op1, %op2
- store <64 x i32> %res, <64 x i32>* %a
- ret void
-}
-
-; Vector i64 sdiv are not legal for NEON so use SVE when available.
-define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
-; CHECK-LABEL: sdiv_v1i64:
-; CHECK: ptrue [[PG:p[0-9]+]].d, vl1
-; CHECK: sdiv z0.d, [[PG]]/m, z0.d, z1.d
-; CHECK: ret
- %res = sdiv <1 x i64> %op1, %op2
- ret <1 x i64> %res
-}
-
-; Vector i64 sdiv are not legal for NEON so use SVE when available.
-define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
-; CHECK-LABEL: sdiv_v2i64:
-; CHECK: ptrue [[PG:p[0-9]+]].d, vl2
-; CHECK: sdiv z0.d, [[PG]]/m, z0.d, z1.d
-; CHECK: ret
- %res = sdiv <2 x i64> %op1, %op2
- ret <2 x i64> %res
-}
-
-define void @sdiv_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
-; CHECK-LABEL: sdiv_v4i64:
-; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
-; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
-; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
-; CHECK: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
-; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
-; CHECK: ret
- %op1 = load <4 x i64>, <4 x i64>* %a
- %op2 = load <4 x i64>, <4 x i64>* %b
- %res = sdiv <4 x i64> %op1, %op2
- store <4 x i64> %res, <4 x i64>* %a
- ret void
-}
-
-define void @sdiv_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
-; CHECK-LABEL: sdiv_v8i64:
-; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
-; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
-; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
-; CHECK: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
-; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
-; CHECK: ret
- %op1 = load <8 x i64>, <8 x i64>* %a
- %op2 = load <8 x i64>, <8 x i64>* %b
- %res = sdiv <8 x i64> %op1, %op2
- store <8 x i64> %res, <8 x i64>* %a
- ret void
-}
-
-define void @sdiv_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
-; CHECK-LABEL: sdiv_v16i64:
-; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
-; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
-; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
-; CHECK: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
-; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
-; CHECK: ret
- %op1 = load <16 x i64>, <16 x i64>* %a
- %op2 = load <16 x i64>, <16 x i64>* %b
- %res = sdiv <16 x i64> %op1, %op2
- store <16 x i64> %res, <16 x i64>* %a
- ret void
-}
-
-define void @sdiv_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
-; CHECK-LABEL: sdiv_v32i64:
-; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
-; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
-; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
-; CHECK: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
-; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
-; CHECK: ret
- %op1 = load <32 x i64>, <32 x i64>* %a
- %op2 = load <32 x i64>, <32 x i64>* %b
- %res = sdiv <32 x i64> %op1, %op2
- store <32 x i64> %res, <32 x i64>* %a
- ret void
-}
-
;
; MUL
;
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
index 6c1831b487f2..ad94b799fbd9 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
@@ -334,4 +334,164 @@ define void @sdiv_v128i16(<128 x i16>* %a, <128 x i16>* %b) #0 {
ret void
}
+; Vector v2i32 sdiv are not legal for NEON so use SVE when available.
+define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+; CHECK-LABEL: sdiv_v2i32:
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),2)]]
+; CHECK: sdiv z0.s, [[PG]]/m, z0.s, z1.s
+; CHECK: ret
+ %res = sdiv <2 x i32> %op1, %op2
+ ret <2 x i32> %res
+}
+
+; Vector v4i32 sdiv are not legal for NEON so use SVE when available.
+define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+; CHECK-LABEL: sdiv_v4i32:
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),4)]]
+; CHECK: sdiv z0.s, [[PG]]/m, z0.s, z1.s
+; CHECK: ret
+ %res = sdiv <4 x i32> %op1, %op2
+ ret <4 x i32> %res
+}
+
+define void @sdiv_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
+; CHECK-LABEL: sdiv_v8i32:
+; VBITS_GE_256: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
+; VBITS_GE_256-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_256-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
+; VBITS_GE_256-NEXT: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
+; VBITS_GE_256-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
+; VBITS_GE_256-NEXT: ret
+ %op1 = load <8 x i32>, <8 x i32>* %a
+ %op2 = load <8 x i32>, <8 x i32>* %b
+ %res = sdiv <8 x i32> %op1, %op2
+ store <8 x i32> %res, <8 x i32>* %a
+ ret void
+}
+
+define void @sdiv_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
+; CHECK-LABEL: sdiv_v16i32:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
+; VBITS_GE_512-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
+; VBITS_GE_512-NEXT: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
+; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
+; VBITS_GE_512-NEXT: ret
+ %op1 = load <16 x i32>, <16 x i32>* %a
+ %op2 = load <16 x i32>, <16 x i32>* %b
+ %res = sdiv <16 x i32> %op1, %op2
+ store <16 x i32> %res, <16 x i32>* %a
+ ret void
+}
+
+define void @sdiv_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
+; CHECK-LABEL: sdiv_v32i32:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
+; VBITS_GE_1024-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
+; VBITS_GE_1024-NEXT: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
+; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
+; VBITS_GE_1024-NEXT: ret
+ %op1 = load <32 x i32>, <32 x i32>* %a
+ %op2 = load <32 x i32>, <32 x i32>* %b
+ %res = sdiv <32 x i32> %op1, %op2
+ store <32 x i32> %res, <32 x i32>* %a
+ ret void
+}
+
+define void @sdiv_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
+; CHECK-LABEL: sdiv_v64i32:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
+; VBITS_GE_2048-NEXT: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
+; VBITS_GE_2048-NEXT: sdiv [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s
+; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
+; VBITS_GE_2048-NEXT: ret
+ %op1 = load <64 x i32>, <64 x i32>* %a
+ %op2 = load <64 x i32>, <64 x i32>* %b
+ %res = sdiv <64 x i32> %op1, %op2
+ store <64 x i32> %res, <64 x i32>* %a
+ ret void
+}
+
+; Vector i64 sdiv are not legal for NEON so use SVE when available.
+define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+; CHECK-LABEL: sdiv_v1i64:
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl1
+; CHECK: sdiv z0.d, [[PG]]/m, z0.d, z1.d
+; CHECK: ret
+ %res = sdiv <1 x i64> %op1, %op2
+ ret <1 x i64> %res
+}
+
+; Vector i64 sdiv are not legal for NEON so use SVE when available.
+define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+; CHECK-LABEL: sdiv_v2i64:
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl2
+; CHECK: sdiv z0.d, [[PG]]/m, z0.d, z1.d
+; CHECK: ret
+ %res = sdiv <2 x i64> %op1, %op2
+ ret <2 x i64> %res
+}
+
+define void @sdiv_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
+; CHECK-LABEL: sdiv_v4i64:
+; VBITS_GE_256: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
+; VBITS_GE_256-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_256-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
+; VBITS_GE_256-NEXT: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
+; VBITS_GE_256-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
+; VBITS_GE_256-NEXT: ret
+ %op1 = load <4 x i64>, <4 x i64>* %a
+ %op2 = load <4 x i64>, <4 x i64>* %b
+ %res = sdiv <4 x i64> %op1, %op2
+ store <4 x i64> %res, <4 x i64>* %a
+ ret void
+}
+
+define void @sdiv_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
+; CHECK-LABEL: sdiv_v8i64:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
+; VBITS_GE_512-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
+; VBITS_GE_512-NEXT: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
+; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
+; VBITS_GE_512-NEXT: ret
+ %op1 = load <8 x i64>, <8 x i64>* %a
+ %op2 = load <8 x i64>, <8 x i64>* %b
+ %res = sdiv <8 x i64> %op1, %op2
+ store <8 x i64> %res, <8 x i64>* %a
+ ret void
+}
+
+define void @sdiv_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
+; CHECK-LABEL: sdiv_v16i64:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
+; VBITS_GE_1024-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
+; VBITS_GE_1024-NEXT: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
+; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
+; VBITS_GE_1024-NEXT: ret
+ %op1 = load <16 x i64>, <16 x i64>* %a
+ %op2 = load <16 x i64>, <16 x i64>* %b
+ %res = sdiv <16 x i64> %op1, %op2
+ store <16 x i64> %res, <16 x i64>* %a
+ ret void
+}
+
+define void @sdiv_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
+; CHECK-LABEL: sdiv_v32i64:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
+; VBITS_GE_2048-NEXT: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
+; VBITS_GE_2048-NEXT: sdiv [[RES:z[0-9]+]].d, [[PG]]/m, [[OP1]].d, [[OP2]].d
+; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
+; VBITS_GE_2048-NEXT: ret
+ %op1 = load <32 x i64>, <32 x i64>* %a
+ %op2 = load <32 x i64>, <32 x i64>* %b
+ %res = sdiv <32 x i64> %op1, %op2
+ store <32 x i64> %res, <32 x i64>* %a
+ ret void
+}
+
attributes #0 = { "target-features"="+sve" }
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