[PATCH] D81669: [PowerPC] Support constrained fp operation for scalar sitofp/uitofp

[Ulrich Weigand via Phabricator via llvm-commits]

uweigand added a comment.

A few comments inline, otherwise this looks good.



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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:8304
   SDValue Mov = DAG.getNode(MovOpc, dl, MVT::f64, Src);
-  return convertIntToFP(Op, Mov, DAG, Subtarget);
+  return convertIntToFP(Op, Mov, DAG, Subtarget, Op.getOperand(0));
 }
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Shouldn't you pass an empty chain to convertIntToFP for non-strict operations?
Or else, given that you pass the full Op, I guess convertIntToFP can retrieve the chain itself?


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Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1587
+def : Pat<(f32 (PPCstrict_fcfidus f64:$A)),
+          (f32 (FCFIDUS f64:$A))>;
+
----------------
Is there any reason for not just matching them in the original patterns via PPCany_... operators like elsewhere?  Also, need to verify the mayRaiseFPException flags for those patterns.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:2440
+def : Pat<(f32 (PPCstrict_fcfidus f64:$A)),
+          (f32 (XSCVUXDSP f64:$A))>;
+
----------------
Same comment as above.


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  https://reviews.llvm.org/D81669/new/

https://reviews.llvm.org/D81669