[PATCH] D68035: [PowerPC] Extend custom lower of vector truncate to handle wider input

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

Other than a couple of minor nits, LGTM. I am so sorry about the delay in reviewing this.



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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:8089
+                      DAG.getConstant(SplitNumElts, DL, VecIdxTy));
+    Op2 = DAG.getNode(ISD::BITCAST, DL, WideVT, Op2);
+  }
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I realize that we don't need to bitcast `Op1` here because it already gets bitcasted below. But I think it is one of those things that a reader looking at this code thinks "Huh? How come only one is bitcasted?" (until they get to the bottom of the function).

So my minor nit here would be to just do both bicasts at the same point below unconditionally. Bitcasting to the same type should not produce a new node.


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Comment at: llvm/test/CodeGen/PowerPC/vec-trunc2.ll:65
+; CHECK-BE-NEXT:    blr
+                                    i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
+%v10 = insertelement <8 x i32> undef, i32 %i1, i32 0
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It's bizarre that the script put the checks inside the signature of the function.


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  https://reviews.llvm.org/D68035/new/

https://reviews.llvm.org/D68035