[llvm] b690c11 - [AMDGPU] Correct DWARF register defintions

[via llvm-commits]

Author: Tony
Date: 2020-08-20T01:15:04Z
New Revision: b690c1157e90b67ecd8f03b902c452ad13defb6f

URL: https://github.com/llvm/llvm-project/commit/b690c1157e90b67ecd8f03b902c452ad13defb6f
DIFF: https://github.com/llvm/llvm-project/commit/b690c1157e90b67ecd8f03b902c452ad13defb6f.diff

LOG: [AMDGPU] Correct DWARF register defintions

- Rename AMDGPU SCC DWARF register to STATUS since the scalar
  condition code is a bit within the STATUS register.

- Correct bit size of the VCC_64 register to 64 which is the size in
  wave64 mode.

Differential Revision: https://reviews.llvm.org/D86259

Added: 
    

Modified: 
    llvm/docs/AMDGPUUsage.rst

Removed: 
    


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diff  --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 478370bb4342..967b667427e0 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -1237,7 +1237,7 @@ mapping.
                                              Registers.
    96-127         *Reserved*                 *Reserved for frequently accessed
                                              registers using DWARF 1-byte ULEB.*
-   128            SCC               32       Scalar Condition Code Register.
+   128            STATUS            32       Status Register.
    129-511        *Reserved*                 *Reserved for future Scalar
                                              Architectural Registers.*
    512            VCC_32            32       Vector Condition Code Register
@@ -1246,7 +1246,7 @@ mapping.
    513-1023       *Reserved*                 *Reserved for future Vector
                                              Architectural Registers when
                                              executing in wavefront 32 mode.*
-   768            VCC_64            32       Vector Condition Code Register
+   768            VCC_64            64       Vector Condition Code Register
                                              when executing in wavefront 64
                                              mode.
    769-1023       *Reserved*                 *Reserved for future Vector