[PATCH] D86204: [SVE] Add ISEL patterns for predicated shifts by an immediate.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm created this revision.
Herald added subscribers: llvm-commits, psnobl, hiraditya, tschuett.
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paulwalker-arm requested review of this revision.

For scalable vector shifts the prediacte is typically all active,
which gets selected to an unpredicated shift by immediate.  When
code generating for fixed length vectors the predicate is based
on the vector length and so additional patterns are required to
make use of SVE's predicated shift by immediate instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D86204

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll

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