[llvm] 7db5124 - [X86][AVX] lowerShuffleWithVTRUNC - avoid unnecessary division in element counts. NFCI.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-08-18T13:48:22+01:00
New Revision: 7db5124736d1b87e938f56c7eaa48f118fd328b0

URL: https://github.com/llvm/llvm-project/commit/7db5124736d1b87e938f56c7eaa48f118fd328b0
DIFF: https://github.com/llvm/llvm-project/commit/7db5124736d1b87e938f56c7eaa48f118fd328b0.diff

LOG: [X86][AVX] lowerShuffleWithVTRUNC - avoid unnecessary division in element counts. NFCI.

(256 / SrcEltBits) == ((2 * EltSizeInBits * NumElts) / (EltSizeInBits * Scale)) == (2 * (NumElts / Scale)) == NumSrcElts

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a929df328e13..27dee97edb2f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -11415,7 +11415,7 @@ static SDValue lowerShuffleAsVTRUNC(const SDLoc &DL, MVT VT, SDValue V1,
     SDValue Src = DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatVT, V1, V2);
 
     MVT SrcSVT = MVT::getIntegerVT(SrcEltBits);
-    MVT SrcVT = MVT::getVectorVT(SrcSVT, 256 / SrcEltBits);
+    MVT SrcVT = MVT::getVectorVT(SrcSVT, NumSrcElts);
     Src = DAG.getBitcast(SrcVT, Src);
 
     if (SrcVT.getVectorNumElements() == NumElts)