[PATCH] D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally created this revision.
cameron.mcinally added reviewers: paulwalker-arm, efriedma, david-arm.
Herald added subscribers: llvm-commits, psnobl, hiraditya, tschuett.
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cameron.mcinally requested review of this revision.

There are no nxv16i8/nxv8i16 SDIV instructions, so these fixed width operations must be promoted to nxv4i32. This required adding an OverrideNEON flag to `LowerToScalableOp(...)`, so that we can make use of the existing scalable lowering for the smaller vectors (e.g. v8i8).

Also notice that a new test file was needed. The existing SDIV tests live in `sve-fixed-length-int-arith.ll`, which uses the legalization-style FileCheck macros. But the complicated lowering of these operations really needs the "end result"-style macros. If this patch is accepted, I'll move the vXi32/vXi64 tests to this new file as well.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D86114

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll

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