[PATCH] D82603: AMDGPU: Implement waterfall loop for MIMG instructions with 256-bit SRsrc

[Changpeng Fang via Phabricator via llvm-commits]

cfang updated this revision to Diff 286071.
cfang added a comment.

A minor change to use the register directly in stead of getting it from the instruction.

NOTE: this is based on the version we have generalized the resource register size based
on the implementation from GISel.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82603/new/

https://reviews.llvm.org/D82603

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/test/CodeGen/AMDGPU/image-sample-waterfall.ll
  llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
  llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
  llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll

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