[PATCH] D77152: [SelectionDAG] Better legalization for FSHL and FSHR

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:148
+    if (Op0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(Op0.getOperand(1)) &&
+        isa<ConstantSDNode>(Op1)) {
+      uint64_t ShlAmt =
----------------
arsenm wrote:
> dyn_cast rather than isa and cast?
I refactored it a little to use isa and getConstantOperandVal, which seems to be the prevailing style in this file.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77152/new/

https://reviews.llvm.org/D77152